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-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td108
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td108
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td33
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td52
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td56
5 files changed, 88 insertions, 269 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index fba39645e43..d19fb2a5398 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -489,40 +489,19 @@ def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
"BLSMSK(32|64)rr",
"BLSR(32|64)rr",
"LEA(16|32|64)(_32)?r",
- "MMX_PABSBrr",
- "MMX_PABSDrr",
- "MMX_PABSWrr",
- "MMX_PADDBirr",
- "MMX_PADDDirr",
- "MMX_PADDQirr",
- "MMX_PADDSBirr",
- "MMX_PADDSWirr",
- "MMX_PADDUSBirr",
- "MMX_PADDUSWirr",
- "MMX_PADDWirr",
- "MMX_PAVGBirr",
- "MMX_PAVGWirr",
- "MMX_PCMPEQBirr",
- "MMX_PCMPEQDirr",
- "MMX_PCMPEQWirr",
- "MMX_PCMPGTBirr",
- "MMX_PCMPGTDirr",
- "MMX_PCMPGTWirr",
- "MMX_PMAXSWirr",
- "MMX_PMAXUBirr",
- "MMX_PMINSWirr",
- "MMX_PMINUBirr",
- "MMX_PSIGNBrr",
- "MMX_PSIGNDrr",
- "MMX_PSIGNWrr",
- "MMX_PSUBBirr",
- "MMX_PSUBDirr",
- "MMX_PSUBQirr",
- "MMX_PSUBSBirr",
- "MMX_PSUBSWirr",
- "MMX_PSUBUSBirr",
- "MMX_PSUBUSWirr",
- "MMX_PSUBWirr",
+ "MMX_PABS(B|D|W)rr",
+ "MMX_PADD(B|D|Q|W)irr",
+ "MMX_PADDS(B|W)irr",
+ "MMX_PADDUS(B|W)irr",
+ "MMX_PAVG(B|W)irr",
+ "MMX_PCMPEQ(B|D|W)irr",
+ "MMX_PCMPGT(B|D|W)irr",
+ "MMX_P(MAX|MIN)SWirr",
+ "MMX_P(MAX|MIN)UBirr",
+ "MMX_PSIGN(B|D|W)rr",
+ "MMX_PSUB(B|D|Q|W)irr",
+ "MMX_PSUBS(B|W)irr",
+ "MMX_PSUBUS(B|W)irr",
"(V?)PABSB(Y?)rr",
"(V?)PABSD(Y?)rr",
"(V?)PABSW(Y?)rr",
@@ -891,12 +870,7 @@ def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
- "MMX_PHADDSWrr",
- "MMX_PHADDWrr",
- "MMX_PHSUBDrr",
- "MMX_PHSUBSWrr",
- "MMX_PHSUBWrr",
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rr",
"(V?)PHADDD(Y?)rr",
"(V?)PHADDSW(Y?)rr",
"(V?)PHADDW(Y?)rr",
@@ -1350,40 +1324,19 @@ def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MMX_PABSBrm",
- "MMX_PABSDrm",
- "MMX_PABSWrm",
- "MMX_PADDBirm",
- "MMX_PADDDirm",
- "MMX_PADDQirm",
- "MMX_PADDSBirm",
- "MMX_PADDSWirm",
- "MMX_PADDUSBirm",
- "MMX_PADDUSWirm",
- "MMX_PADDWirm",
- "MMX_PAVGBirm",
- "MMX_PAVGWirm",
- "MMX_PCMPEQBirm",
- "MMX_PCMPEQDirm",
- "MMX_PCMPEQWirm",
- "MMX_PCMPGTBirm",
- "MMX_PCMPGTDirm",
- "MMX_PCMPGTWirm",
- "MMX_PMAXSWirm",
- "MMX_PMAXUBirm",
- "MMX_PMINSWirm",
- "MMX_PMINUBirm",
- "MMX_PSIGNBrm",
- "MMX_PSIGNDrm",
- "MMX_PSIGNWrm",
- "MMX_PSUBBirm",
- "MMX_PSUBDirm",
- "MMX_PSUBQirm",
- "MMX_PSUBSBirm",
- "MMX_PSUBSWirm",
- "MMX_PSUBUSBirm",
- "MMX_PSUBUSWirm",
- "MMX_PSUBWirm",
+ "MMX_PABS(B|D|W)rm",
+ "MMX_PADD(B|D|Q|W)irm",
+ "MMX_PADDS(B|W)irm",
+ "MMX_PADDUS(B|W)irm",
+ "MMX_PAVG(B|W)irm",
+ "MMX_PCMPEQ(B|D|W)irm",
+ "MMX_PCMPGT(B|D|W)irm",
+ "MMX_P(MAX|MIN)SWirm",
+ "MMX_P(MAX|MIN)UBirm",
+ "MMX_PSIGN(B|D|W)rm",
+ "MMX_PSUB(B|D|Q|W)irm",
+ "MMX_PSUBS(B|W)irm",
+ "MMX_PSUBUS(B|W)irm",
"MOVBE(16|32|64)rm",
"(V?)PABSBrm",
"(V?)PABSDrm",
@@ -1840,12 +1793,7 @@ def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
- "MMX_PHADDSWrm",
- "MMX_PHADDWrm",
- "MMX_PHSUBDrm",
- "MMX_PHSUBSWrm",
- "MMX_PHSUBWrm",
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rm",
"(V?)PHADDDrm",
"(V?)PHADDSWrm",
"(V?)PHADDWrm",
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 495ae29e4c7..8ac2051ffe6 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -852,40 +852,19 @@ def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr",
"BLSMSK(32|64)rr",
"BLSR(32|64)rr",
"LEA(16|32|64)(_32)?r",
- "MMX_PABSBrr",
- "MMX_PABSDrr",
- "MMX_PABSWrr",
- "MMX_PADDBirr",
- "MMX_PADDDirr",
- "MMX_PADDQirr",
- "MMX_PADDSBirr",
- "MMX_PADDSWirr",
- "MMX_PADDUSBirr",
- "MMX_PADDUSWirr",
- "MMX_PADDWirr",
- "MMX_PAVGBirr",
- "MMX_PAVGWirr",
- "MMX_PCMPEQBirr",
- "MMX_PCMPEQDirr",
- "MMX_PCMPEQWirr",
- "MMX_PCMPGTBirr",
- "MMX_PCMPGTDirr",
- "MMX_PCMPGTWirr",
- "MMX_PMAXSWirr",
- "MMX_PMAXUBirr",
- "MMX_PMINSWirr",
- "MMX_PMINUBirr",
- "MMX_PSIGNBrr",
- "MMX_PSIGNDrr",
- "MMX_PSIGNWrr",
- "MMX_PSUBBirr",
- "MMX_PSUBDirr",
- "MMX_PSUBQirr",
- "MMX_PSUBSBirr",
- "MMX_PSUBSWirr",
- "MMX_PSUBUSBirr",
- "MMX_PSUBUSWirr",
- "MMX_PSUBWirr",
+ "MMX_PABS(B|D|W)rr",
+ "MMX_PADD(B|D|Q|W)irr",
+ "MMX_PADDS(B|W)irr",
+ "MMX_PADDUS(B|W)irr",
+ "MMX_PAVG(B|W)irr",
+ "MMX_PCMPEQ(B|D|W)irr",
+ "MMX_PCMPGT(B|D|W)irr",
+ "MMX_P(MAX|MIN)SWirr",
+ "MMX_P(MAX|MIN)UBirr",
+ "MMX_PSIGN(B|D|W)rr",
+ "MMX_PSUB(B|D|Q|W)irr",
+ "MMX_PSUBS(B|W)irr",
+ "MMX_PSUBUS(B|W)irr",
"(V?)PABSB(Y?)rr",
"(V?)PABSD(Y?)rr",
"(V?)PABSW(Y?)rr",
@@ -1210,40 +1189,19 @@ def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MMX_PABSBrm",
- "MMX_PABSDrm",
- "MMX_PABSWrm",
- "MMX_PADDBirm",
- "MMX_PADDDirm",
- "MMX_PADDQirm",
- "MMX_PADDSBirm",
- "MMX_PADDSWirm",
- "MMX_PADDUSBirm",
- "MMX_PADDUSWirm",
- "MMX_PADDWirm",
- "MMX_PAVGBirm",
- "MMX_PAVGWirm",
- "MMX_PCMPEQBirm",
- "MMX_PCMPEQDirm",
- "MMX_PCMPEQWirm",
- "MMX_PCMPGTBirm",
- "MMX_PCMPGTDirm",
- "MMX_PCMPGTWirm",
- "MMX_PMAXSWirm",
- "MMX_PMAXUBirm",
- "MMX_PMINSWirm",
- "MMX_PMINUBirm",
- "MMX_PSIGNBrm",
- "MMX_PSIGNDrm",
- "MMX_PSIGNWrm",
- "MMX_PSUBBirm",
- "MMX_PSUBDirm",
- "MMX_PSUBQirm",
- "MMX_PSUBSBirm",
- "MMX_PSUBSWirm",
- "MMX_PSUBUSBirm",
- "MMX_PSUBUSWirm",
- "MMX_PSUBWirm",
+ "MMX_PABS(B|D|W)rm",
+ "MMX_PADD(B|D|Q|W)irm",
+ "MMX_PADDS(B|W)irm",
+ "MMX_PADDUS(B|W)irm",
+ "MMX_PAVG(B|W)irm",
+ "MMX_PCMPEQ(B|D|W)irm",
+ "MMX_PCMPGT(B|D|W)irm",
+ "MMX_P(MAX|MIN)SWirm",
+ "MMX_P(MAX|MIN)UBirm",
+ "MMX_PSIGN(B|D|W)rm",
+ "MMX_PSUB(B|D|Q|W)irm",
+ "MMX_PSUBS(B|W)irm",
+ "MMX_PSUBUS(B|W)irm",
"MOVBE(16|32|64)rm")>;
def HWWriteResGroup16_1 : SchedWriteRes<[HWPort23,HWPort15]> {
@@ -1877,12 +1835,7 @@ def HWWriteResGroup56 : SchedWriteRes<[HWPort5,HWPort15]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDDrr",
- "MMX_PHADDSWrr",
- "MMX_PHADDWrr",
- "MMX_PHSUBDrr",
- "MMX_PHSUBSWrr",
- "MMX_PHSUBWrr",
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rr",
"(V?)PHADDD(Y?)rr",
"(V?)PHADDSW(Y?)rr",
"(V?)PHADDW(Y?)rr",
@@ -1972,12 +1925,7 @@ def HWWriteResGroup64 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDDrm",
- "MMX_PHADDSWrm",
- "MMX_PHADDWrm",
- "MMX_PHSUBDrm",
- "MMX_PHSUBSWrm",
- "MMX_PHSUBWrm")>;
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rm")>;
def HWWriteResGroup64_1 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
let Latency = 10;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index d46fdb10735..6662d5fc67b 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -325,14 +325,13 @@ def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP",
"FFREE",
"FINCSTP",
"FNOP",
- "INSERTPSrr",
"LD_Frr",
"RETQ",
"ST_FPrr",
"ST_Frr",
"VEXTRACTF128rr",
"VINSERTF128rr",
- "VINSERTPSrr",
+ "(V?)INSERTPSrr",
"(V?)MOV64toPQIrr",
"(V?)MOVDDUP(Y?)rr",
"(V?)MOVDI2PDIrr",
@@ -381,14 +380,10 @@ def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr",
- "MMX_PABSDrr",
- "MMX_PABSWrr",
+def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABS(B|D|W)rr",
"MMX_PADDQirr",
"MMX_PALIGNRrri",
- "MMX_PSIGNBrr",
- "MMX_PSIGNDrr",
- "MMX_PSIGNWrr",
+ "MMX_PSIGN(B|D|W)rr",
"(V?)PABSBrr",
"(V?)PABSDrr",
"(V?)PABSWrr",
@@ -685,12 +680,7 @@ def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDDrr",
- "MMX_PHADDSWrr",
- "MMX_PHADDWrr",
- "MMX_PHSUBDrr",
- "MMX_PHSUBSWrr",
- "MMX_PHSUBWrr",
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rr",
"(V?)PHADDDrr",
"(V?)PHADDSWrr",
"(V?)PHADDWrr",
@@ -1012,14 +1002,10 @@ def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm",
- "MMX_PABSDrm",
- "MMX_PABSWrm",
+def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABS(B|D|W)rm",
"MMX_PALIGNRrmi",
"MMX_PSHUFBrm",
- "MMX_PSIGNBrm",
- "MMX_PSIGNDrm",
- "MMX_PSIGNWrm")>;
+ "MMX_PSIGN(B|D|W)rm")>;
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 6;
@@ -1385,12 +1371,7 @@ def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDDrm",
- "MMX_PHADDSWrm",
- "MMX_PHADDWrm",
- "MMX_PHSUBDrm",
- "MMX_PHSUBSWrm",
- "MMX_PHSUBWrm")>;
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PH(ADD|SUB)(D|SW|W)rm")>;
def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 8;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 1d25b208b35..c397a816cfb 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -505,23 +505,13 @@ def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP",
"FNOP",
"MMX_MOVQ64rr",
- "MMX_PABSBrr",
- "MMX_PABSDrr",
- "MMX_PABSWrr",
- "MMX_PADDBirr",
- "MMX_PADDDirr",
- "MMX_PADDQirr",
- "MMX_PADDWirr",
+ "MMX_PABS(B|D|W)rr",
+ "MMX_PADD(B|D|Q|W)irr",
"MMX_PANDNirr",
"MMX_PANDirr",
"MMX_PORirr",
- "MMX_PSIGNBrr",
- "MMX_PSIGNDrr",
- "MMX_PSIGNWrr",
- "MMX_PSUBBirr",
- "MMX_PSUBDirr",
- "MMX_PSUBQirr",
- "MMX_PSUBWirr",
+ "MMX_PSIGN(B|D|W)rr",
+ "MMX_PSUB(B|D|Q|W)irr",
"MMX_PXORirr")>;
def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
@@ -935,8 +925,7 @@ def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PHADDSWrr",
- "MMX_PHSUBSWrr")>;
+def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 3;
@@ -951,10 +940,7 @@ def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDDrr",
- "MMX_PHADDWrr",
- "MMX_PHSUBDrr",
- "MMX_PHSUBWrr")>;
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PH(ADD|SUB)(D|W)rr")>;
def SKLWriteResGroup38 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 3;
@@ -1366,23 +1352,13 @@ def SKLWriteResGroup73 : SchedWriteRes<[SKLPort23,SKLPort05]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABSBrm",
- "MMX_PABSDrm",
- "MMX_PABSWrm",
- "MMX_PADDBirm",
- "MMX_PADDDirm",
- "MMX_PADDQirm",
- "MMX_PADDWirm",
+def: InstRW<[SKLWriteResGroup73], (instregex "MMX_PABS(B|D|W)rm",
+ "MMX_PADD(B|D|Q|W)irm",
"MMX_PANDNirm",
"MMX_PANDirm",
"MMX_PORirm",
- "MMX_PSIGNBrm",
- "MMX_PSIGNDrm",
- "MMX_PSIGNWrm",
- "MMX_PSUBBirm",
- "MMX_PSUBDirm",
- "MMX_PSUBQirm",
- "MMX_PSUBWirm",
+ "MMX_PSIGN(B|D|W)rm",
+ "MMX_PSUB(B|D|Q|W)irm",
"MMX_PXORirm")>;
def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
@@ -1933,18 +1909,14 @@ def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PHADDSWrm",
- "MMX_PHSUBSWrm")>;
+def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
let Latency = 8;
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm",
- "MMX_PHADDWrm",
- "MMX_PHSUBDrm",
- "MMX_PHSUBWrm")>;
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PH(ADD|SUB)(D|W)rm")>;
def SKLWriteResGroup114 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237,SKLPort01]> {
let Latency = 8;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 9353955cc3f..d72e18db7c9 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -411,7 +411,6 @@ def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
}
def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"COM_FST0r",
- "INSERTPSrr",
"KMOVBkr",
"KMOVDkr",
"KMOVQkr",
@@ -476,8 +475,7 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"UNPCKLPSrr",
"VBROADCASTI32X2Z128r",
"VBROADCASTSSrr",
- "VINSERTPSZrr",
- "VINSERTPSrr",
+ "(V?)INSERTPS(Z?)rr",
"VMOV64toPQIZrr",
"VMOV64toPQIrr",
"VMOVDDUPYrr",
@@ -968,23 +966,13 @@ def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
def: InstRW<[SKXWriteResGroup6], (instregex "FINCSTP",
"FNOP",
"MMX_MOVQ64rr",
- "MMX_PABSBrr",
- "MMX_PABSDrr",
- "MMX_PABSWrr",
- "MMX_PADDBirr",
- "MMX_PADDDirr",
- "MMX_PADDQirr",
- "MMX_PADDWirr",
+ "MMX_PABS(B|D|W)rr",
+ "MMX_PADD(B|D|Q|W)irr",
"MMX_PANDNirr",
"MMX_PANDirr",
"MMX_PORirr",
- "MMX_PSIGNBrr",
- "MMX_PSIGNDrr",
- "MMX_PSIGNWrr",
- "MMX_PSUBBirr",
- "MMX_PSUBDirr",
- "MMX_PSUBQirr",
- "MMX_PSUBWirr",
+ "MMX_PSIGN(B|D|W)rr",
+ "MMX_PSUB(B|D|Q|W)irr",
"MMX_PXORirr")>;
def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
@@ -1988,8 +1976,7 @@ def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PHADDSWrr",
- "MMX_PHSUBSWrr")>;
+def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
let Latency = 3;
@@ -2008,10 +1995,7 @@ def SKXWriteResGroup39 : SchedWriteRes<[SKXPort5,SKXPort05]> {
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDDrr",
- "MMX_PHADDWrr",
- "MMX_PHSUBDrr",
- "MMX_PHSUBWrr")>;
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PH(ADD|SUB)(D|W)rr")>;
def SKXWriteResGroup40 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 3;
@@ -2900,23 +2884,13 @@ def SKXWriteResGroup77 : SchedWriteRes<[SKXPort23,SKXPort05]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABSBrm",
- "MMX_PABSDrm",
- "MMX_PABSWrm",
- "MMX_PADDBirm",
- "MMX_PADDDirm",
- "MMX_PADDQirm",
- "MMX_PADDWirm",
+def: InstRW<[SKXWriteResGroup77], (instregex "MMX_PABS(B|D|W)rm",
+ "MMX_PADD(B|D|Q|W)irm",
"MMX_PANDNirm",
"MMX_PANDirm",
"MMX_PORirm",
- "MMX_PSIGNBrm",
- "MMX_PSIGNDrm",
- "MMX_PSIGNWrm",
- "MMX_PSUBBirm",
- "MMX_PSUBDirm",
- "MMX_PSUBQirm",
- "MMX_PSUBWirm",
+ "MMX_PSIGN(B|D|W)rm",
+ "MMX_PSUB(B|D|Q|W)irm",
"MMX_PXORirm")>;
def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
@@ -4169,18 +4143,14 @@ def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
-def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PHADDSWrm",
- "MMX_PHSUBSWrm")>;
+def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
def SKXWriteResGroup124 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort05]> {
let Latency = 8;
let NumMicroOps = 4;
let ResourceCycles = [2,1,1];
}
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDDrm",
- "MMX_PHADDWrm",
- "MMX_PHSUBDrm",
- "MMX_PHSUBWrm")>;
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PH(ADD|SUB)(D|W)rm")>;
def SKXWriteResGroup125 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237,SKXPort015]> {
let Latency = 8;
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