diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFastISel.cpp | 4 |
2 files changed, 6 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index ade9561e879..1e31c74f179 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2218,11 +2218,10 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, int CondCode = CD->getSExtValue(); if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE || - CondCode >= ICmpInst::Predicate::BAD_ICMP_PREDICATE) + CondCode >= ICmpInst::Predicate::BAD_ICMP_PREDICATE) return DAG.getUNDEF(VT); - ICmpInst::Predicate IcInput = - static_cast<ICmpInst::Predicate>(CondCode); + ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode); ISD::CondCode CCOpcode = getICmpCondCode(IcInput); return DAG.getNode(AMDGPUISD::SETCC, DL, VT, Op.getOperand(1), Op.getOperand(2), DAG.getCondCode(CCOpcode)); @@ -2232,11 +2231,10 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, int CondCode = CD->getSExtValue(); if (CondCode <= FCmpInst::Predicate::FCMP_FALSE || - CondCode >= FCmpInst::Predicate::FCMP_TRUE) + CondCode >= FCmpInst::Predicate::FCMP_TRUE) return DAG.getUNDEF(VT); - FCmpInst::Predicate IcInput = - static_cast<FCmpInst::Predicate>(CondCode); + FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode); ISD::CondCode CCOpcode = getFCmpCondCode(IcInput); return DAG.getNode(AMDGPUISD::SETCC, DL, VT, Op.getOperand(1), Op.getOperand(2), DAG.getCondCode(CCOpcode)); diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp index b69acc5e5e7..49f96260ae6 100644 --- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -580,8 +580,8 @@ bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break; } - auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(Opc), ResultReg); + auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), + ResultReg); // If we have an index register defined we use it in the store inst, // otherwise we use X0 as base as it makes the vector instructions to |
