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-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index dcf25c629d5..e0637094a06 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -32741,8 +32741,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
SDValue AndNode = Cond.getOperand(0);
if (AndNode.getOpcode() == ISD::AND && CC == ISD::SETEQ &&
isNullConstant(Cond.getOperand(1)) &&
- isa<ConstantSDNode>(AndNode.getOperand(1)) &&
- cast<ConstantSDNode>(AndNode.getOperand(1))->getAPIntValue() == 1) {
+ isOneConstant(AndNode.getOperand(1))) {
// LHS and RHS swapped due to
// setcc outputting 1 when AND resulted in 0 and vice versa.
AndNode = DAG.getZExtOrTrunc(AndNode, DL, MVT::i8);
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