diff options
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.h | 2 |
2 files changed, 8 insertions, 18 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 0df268d1f99..32e1ba30b0f 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3627,18 +3627,9 @@ static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode, MemSDNode *M, SelectionDAG &DAG, + ArrayRef<SDValue> Ops, bool IsIntrinsic) const { SDLoc DL(M); - SmallVector<SDValue, 10> Ops; - Ops.reserve(M->getNumOperands()); - - Ops.push_back(M->getOperand(0)); - if (IsIntrinsic) - Ops.push_back(DAG.getConstant(Opcode, DL, MVT::i32)); - - // Skip 1, as it is the intrinsic ID. - for (unsigned I = 2, E = M->getNumOperands(); I != E; ++I) - Ops.push_back(M->getOperand(I)); bool Unpacked = Subtarget->hasUnpackedD16VMem(); EVT LoadVT = M->getValueType(0); @@ -5099,20 +5090,16 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, EVT IntVT = VT.changeTypeToInteger(); auto *M = cast<MemSDNode>(Op); EVT LoadVT = Op.getValueType(); - bool IsD16 = LoadVT.getScalarType() == MVT::f16; - if (IsD16) - return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG); + if (LoadVT.getScalarType() == MVT::f16) + return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, + M, DAG, Ops); return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT, M->getMemOperand()); } case Intrinsic::amdgcn_tbuffer_load: { MemSDNode *M = cast<MemSDNode>(Op); EVT LoadVT = Op.getValueType(); - bool IsD16 = LoadVT.getScalarType() == MVT::f16; - if (IsD16) { - return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16, M, DAG); - } SDValue Ops[] = { Op.getOperand(0), // Chain @@ -5127,6 +5114,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, Op.getOperand(10) // slc }; + if (LoadVT.getScalarType() == MVT::f16) + return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16, + M, DAG, Ops); return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL, Op->getVTList(), Ops, LoadVT, M->getMemOperand()); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index 5b3d49b3d8e..827c3695b61 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -81,7 +81,7 @@ private: SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, - SelectionDAG &DAG, + SelectionDAG &DAG, ArrayRef<SDValue> Ops, bool IsIntrinsic = false) const; SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const; |
