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-rw-r--r--llvm/lib/Target/Mips/MipsCCState.cpp61
-rw-r--r--llvm/lib/Target/Mips/MipsCCState.h33
-rw-r--r--llvm/lib/Target/Mips/MipsCallingConv.td10
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.cpp74
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.h27
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterInfo.cpp4
6 files changed, 194 insertions, 15 deletions
diff --git a/llvm/lib/Target/Mips/MipsCCState.cpp b/llvm/lib/Target/Mips/MipsCCState.cpp
index cb9f676c237..6a03ee9927d 100644
--- a/llvm/lib/Target/Mips/MipsCCState.cpp
+++ b/llvm/lib/Target/Mips/MipsCCState.cpp
@@ -51,6 +51,22 @@ static bool originalTypeIsF128(const Type *Ty, const char *Func) {
return (Func && Ty->isIntegerTy(128) && isF128SoftLibCall(Func));
}
+/// Return true if the original type was vXfXX.
+static bool originalEVTTypeIsVectorFloat(EVT Ty) {
+ if (Ty.isVector() && Ty.getVectorElementType().isFloatingPoint())
+ return true;
+
+ return false;
+}
+
+/// Return true if the original type was vXfXX / vXfXX.
+static bool originalTypeIsVectorFloat(const Type * Ty) {
+ if (Ty->isVectorTy() && Ty->isFPOrFPVectorTy())
+ return true;
+
+ return false;
+}
+
MipsCCState::SpecialCallingConvType
MipsCCState::getSpecialCallingConvForCallee(const SDNode *Callee,
const MipsSubtarget &Subtarget) {
@@ -78,8 +94,8 @@ void MipsCCState::PreAnalyzeCallResultForF128(
}
}
-/// Identify lowered values that originated from f128 arguments and record
-/// this for use by RetCC_MipsN.
+/// Identify lowered values that originated from f128 or float arguments and
+/// record this for use by RetCC_MipsN.
void MipsCCState::PreAnalyzeReturnForF128(
const SmallVectorImpl<ISD::OutputArg> &Outs) {
const MachineFunction &MF = getMachineFunction();
@@ -91,23 +107,44 @@ void MipsCCState::PreAnalyzeReturnForF128(
}
}
-/// Identify lowered values that originated from f128 arguments and record
+/// Identify lower values that originated from vXfXX and record
/// this.
+void MipsCCState::PreAnalyzeCallResultForVectorFloat(
+ const SmallVectorImpl<ISD::InputArg> &Ins, const Type *RetTy) {
+ for (unsigned i = 0; i < Ins.size(); ++i) {
+ OriginalRetWasFloatVector.push_back(originalTypeIsVectorFloat(RetTy));
+ }
+}
+
+/// Identify lowered values that originated from vXfXX arguments and record
+/// this.
+void MipsCCState::PreAnalyzeReturnForVectorFloat(
+ const SmallVectorImpl<ISD::OutputArg> &Outs) {
+ for (unsigned i = 0; i < Outs.size(); ++i) {
+ ISD::OutputArg Out = Outs[i];
+ OriginalRetWasFloatVector.push_back(
+ originalEVTTypeIsVectorFloat(Out.ArgVT));
+ }
+}
+
+/// Identify lowered values that originated from f128, float and sret to vXfXX
+/// arguments and record this.
void MipsCCState::PreAnalyzeCallOperands(
const SmallVectorImpl<ISD::OutputArg> &Outs,
std::vector<TargetLowering::ArgListEntry> &FuncArgs,
const char *Func) {
for (unsigned i = 0; i < Outs.size(); ++i) {
- OriginalArgWasF128.push_back(
- originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, Func));
- OriginalArgWasFloat.push_back(
- FuncArgs[Outs[i].OrigArgIndex].Ty->isFloatingPointTy());
+ TargetLowering::ArgListEntry FuncArg = FuncArgs[Outs[i].OrigArgIndex];
+
+ OriginalArgWasF128.push_back(originalTypeIsF128(FuncArg.Ty, Func));
+ OriginalArgWasFloat.push_back(FuncArg.Ty->isFloatingPointTy());
+ OriginalArgWasFloatVector.push_back(FuncArg.Ty->isVectorTy());
CallOperandIsFixed.push_back(Outs[i].IsFixed);
}
}
-/// Identify lowered values that originated from f128 arguments and record
-/// this.
+/// Identify lowered values that originated from f128, float and vXfXX arguments
+/// and record this.
void MipsCCState::PreAnalyzeFormalArgumentsForF128(
const SmallVectorImpl<ISD::InputArg> &Ins) {
const MachineFunction &MF = getMachineFunction();
@@ -120,6 +157,7 @@ void MipsCCState::PreAnalyzeFormalArgumentsForF128(
if (Ins[i].Flags.isSRet()) {
OriginalArgWasF128.push_back(false);
OriginalArgWasFloat.push_back(false);
+ OriginalArgWasFloatVector.push_back(false);
continue;
}
@@ -129,5 +167,10 @@ void MipsCCState::PreAnalyzeFormalArgumentsForF128(
OriginalArgWasF128.push_back(
originalTypeIsF128(FuncArg->getType(), nullptr));
OriginalArgWasFloat.push_back(FuncArg->getType()->isFloatingPointTy());
+
+ // The MIPS vector ABI exhibits a corner case of sorts or quirk; if the
+ // first argument is actually an SRet pointer to a vector, then the next
+ // argument slot is $a2.
+ OriginalArgWasFloatVector.push_back(FuncArg->getType()->isVectorTy());
}
}
diff --git a/llvm/lib/Target/Mips/MipsCCState.h b/llvm/lib/Target/Mips/MipsCCState.h
index 77ecc65b2ee..27901699480 100644
--- a/llvm/lib/Target/Mips/MipsCCState.h
+++ b/llvm/lib/Target/Mips/MipsCCState.h
@@ -45,16 +45,33 @@ private:
const char *Func);
/// Identify lowered values that originated from f128 arguments and record
- /// this.
+ /// this for use by RetCC_MipsN.
void
PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
+ void
+ PreAnalyzeCallResultForVectorFloat(const SmallVectorImpl<ISD::InputArg> &Ins,
+ const Type *RetTy);
+
+ void PreAnalyzeFormalArgumentsForVectorFloat(
+ const SmallVectorImpl<ISD::InputArg> &Ins);
+
+ void
+ PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
+
/// Records whether the value has been lowered from an f128.
SmallVector<bool, 4> OriginalArgWasF128;
/// Records whether the value has been lowered from float.
SmallVector<bool, 4> OriginalArgWasFloat;
+ /// Records whether the value has been lowered from a floating point vector.
+ SmallVector<bool, 4> OriginalArgWasFloatVector;
+
+ /// Records whether the return value has been lowered from a floating point
+ /// vector.
+ SmallVector<bool, 4> OriginalRetWasFloatVector;
+
/// Records whether the value was a fixed argument.
/// See ISD::OutputArg::IsFixed,
SmallVector<bool, 4> CallOperandIsFixed;
@@ -78,6 +95,7 @@ public:
CCState::AnalyzeCallOperands(Outs, Fn);
OriginalArgWasF128.clear();
OriginalArgWasFloat.clear();
+ OriginalArgWasFloatVector.clear();
CallOperandIsFixed.clear();
}
@@ -96,31 +114,38 @@ public:
CCState::AnalyzeFormalArguments(Ins, Fn);
OriginalArgWasFloat.clear();
OriginalArgWasF128.clear();
+ OriginalArgWasFloatVector.clear();
}
void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
CCAssignFn Fn, const Type *RetTy,
const char *Func) {
PreAnalyzeCallResultForF128(Ins, RetTy, Func);
+ PreAnalyzeCallResultForVectorFloat(Ins, RetTy);
CCState::AnalyzeCallResult(Ins, Fn);
OriginalArgWasFloat.clear();
OriginalArgWasF128.clear();
+ OriginalArgWasFloatVector.clear();
}
void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
CCAssignFn Fn) {
PreAnalyzeReturnForF128(Outs);
+ PreAnalyzeReturnForVectorFloat(Outs);
CCState::AnalyzeReturn(Outs, Fn);
OriginalArgWasFloat.clear();
OriginalArgWasF128.clear();
+ OriginalArgWasFloatVector.clear();
}
bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
CCAssignFn Fn) {
PreAnalyzeReturnForF128(ArgsFlags);
+ PreAnalyzeReturnForVectorFloat(ArgsFlags);
bool Return = CCState::CheckReturn(ArgsFlags, Fn);
OriginalArgWasFloat.clear();
OriginalArgWasF128.clear();
+ OriginalArgWasFloatVector.clear();
return Return;
}
@@ -128,6 +153,12 @@ public:
bool WasOriginalArgFloat(unsigned ValNo) {
return OriginalArgWasFloat[ValNo];
}
+ bool WasOriginalArgVectorFloat(unsigned ValNo) const {
+ return OriginalArgWasFloatVector[ValNo];
+ }
+ bool WasOriginalRetVectorFloat(unsigned ValNo) const {
+ return OriginalRetWasFloatVector[ValNo];
+ }
bool IsCallOperandFixed(unsigned ValNo) { return CallOperandIsFixed[ValNo]; }
SpecialCallingConvType getSpecialCallingConv() { return SpecialCallingConv; }
};
diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td
index a57cb7badc1..b5df78f89a6 100644
--- a/llvm/lib/Target/Mips/MipsCallingConv.td
+++ b/llvm/lib/Target/Mips/MipsCallingConv.td
@@ -37,6 +37,10 @@ class CCIfOrigArgWasF128<CCAction A>
class CCIfArgIsVarArg<CCAction A>
: CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>;
+/// Match if the return was a floating point vector.
+class CCIfOrigArgWasNotVectorFloat<CCAction A>
+ : CCIf<"!static_cast<MipsCCState *>(&State)"
+ "->WasOriginalRetVectorFloat(ValNo)", A>;
/// Match if the special calling conv is the specified value.
class CCIfSpecialCallingConv<string CC, CCAction A>
@@ -93,8 +97,10 @@ def RetCC_MipsO32 : CallingConv<[
// Promote i1/i8/i16 return values to i32.
CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
- // i32 are returned in registers V0, V1, A0, A1
- CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
+ // i32 are returned in registers V0, V1, A0, A1, unless the original return
+ // type was a vector of floats.
+ CCIfOrigArgWasNotVectorFloat<CCIfType<[i32],
+ CCAssignToReg<[V0, V1, A0, A1]>>>,
// f32 are returned in registers F0, F2
CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index ce7dd09f429..f2193013b7a 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -71,6 +71,48 @@ static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
return true;
}
+// The MIPS MSA ABI passes vector arguments in the integer register set.
+// The number of integer registers used is dependant on the ABI used.
+MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
+ if (VT.isVector() && Subtarget.hasMSA())
+ return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
+ return MipsTargetLowering::getRegisterType(VT);
+}
+
+MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
+ EVT VT) const {
+ if (VT.isVector()) {
+ if (Subtarget.isABI_O32()) {
+ return MVT::i32;
+ } else {
+ return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
+ }
+ }
+ return MipsTargetLowering::getRegisterType(Context, VT);
+}
+
+unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
+ EVT VT) const {
+ if (VT.isVector())
+ return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
+ 1U);
+ return MipsTargetLowering::getNumRegisters(Context, VT);
+}
+
+unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
+ LLVMContext &Context, EVT VT, EVT &IntermediateVT,
+ unsigned &NumIntermediates, MVT &RegisterVT) const {
+
+ // Break down vector types to either 2 i64s or 4 i32s.
+ RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
+ IntermediateVT = RegisterVT;
+ NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
+ ? VT.getVectorNumElements()
+ : VT.getSizeInBits() / RegisterVT.getSizeInBits();
+
+ return NumIntermediates;
+}
+
SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
@@ -2552,6 +2594,11 @@ SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
// not used, it must be shadowed. If only A3 is available, shadow it and
// go to stack.
+// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
+// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
+// with the remainder spilled to the stack.
+// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
+// spilling the remainder to the stack.
//
// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
//===----------------------------------------------------------------------===//
@@ -2563,8 +2610,13 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
State.getMachineFunction().getSubtarget());
static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
+
+ const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
+
static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
+ static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
+
// Do not process byval args here.
if (ArgFlags.isByVal())
return true;
@@ -2602,8 +2654,26 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
State.getFirstUnallocated(F32Regs) != ValNo;
unsigned OrigAlign = ArgFlags.getOrigAlign();
bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
-
- if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
+ bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
+
+ // The MIPS vector ABI for floats passes them in a pair of registers
+ if (ValVT == MVT::i32 && isVectorFloat) {
+ // This is the start of an vector that was scalarized into an unknown number
+ // of components. It doesn't matter how many there are. Allocate one of the
+ // notional 8 byte aligned registers which map onto the argument stack, and
+ // shadow the register lost to alignment requirements.
+ if (ArgFlags.isSplit()) {
+ Reg = State.AllocateReg(FloatVectorIntRegs);
+ if (Reg == Mips::A2)
+ State.AllocateReg(Mips::A1);
+ else if (Reg == 0)
+ State.AllocateReg(Mips::A3);
+ } else {
+ // If we're an intermediate component of the split, we can just attempt to
+ // allocate a register directly.
+ Reg = State.AllocateReg(IntRegs);
+ }
+ } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Reg = State.AllocateReg(IntRegs);
// If this is the first part of an i64 arg,
// the allocated register must be either A0 or A2.
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 2dcafd51061..0e47ed38f42 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -248,6 +248,33 @@ namespace llvm {
bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override;
+ /// Return the register type for a given MVT, ensuring vectors are treated
+ /// as a series of gpr sized integers.
+ virtual MVT getRegisterTypeForCallingConv(MVT VT) const override;
+
+ /// Return the register type for a given MVT, ensuring vectors are treated
+ /// as a series of gpr sized integers.
+ virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
+ EVT VT) const override;
+
+ /// Return the number of registers for a given MVT, ensuring vectors are
+ /// treated as a series of gpr sized integers.
+ virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
+ EVT VT) const override;
+
+ /// Break down vectors to the correct number of gpr sized integers.
+ virtual unsigned getVectorTypeBreakdownForCallingConv(
+ LLVMContext &Context, EVT VT, EVT &IntermediateVT,
+ unsigned &NumIntermediates, MVT &RegisterVT) const override;
+
+ /// Return the correct alignment for the current calling convention.
+ virtual unsigned
+ getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override {
+ if (ArgTy->isVectorTy())
+ return std::min(DL.getABITypeAlignment(ArgTy), 8U);
+ return DL.getABITypeAlignment(ArgTy);
+ }
+
ISD::NodeType getExtendForAtomicOps() const override {
return ISD::SIGN_EXTEND;
}
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index 65be350f259..de3389b5a6b 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -286,7 +286,9 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
<< "spOffset : " << spOffset << "\n"
- << "stackSize : " << stackSize << "\n");
+ << "stackSize : " << stackSize << "\n"
+ << "alignment : "
+ << MF.getFrameInfo().getObjectAlignment(FrameIndex) << "\n");
eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
}
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