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-rw-r--r--llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp8
-rw-r--r--llvm/lib/Target/Alpha/AlphaISelPattern.cpp64
-rw-r--r--llvm/lib/Target/Alpha/AlphaInstrInfo.td19
3 files changed, 61 insertions, 30 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 348453bb4d8..acfeb9174cf 100644
--- a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -119,7 +119,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
case MachineOperand::MO_MachineBasicBlock: {
MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
- O << "$LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
+ O << "LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
<< "_" << MBBOp->getNumber() << "\t" << CommentString << " "
<< MBBOp->getBasicBlock()->getName();
return;
@@ -169,7 +169,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
// Print out labels for the function.
O << "\t.text\n";
- emitAlignment(4);
+ emitAlignment(3);
O << "\t.globl\t" << CurrentFnName << "\n";
O << "\t.ent\t" << CurrentFnName << "\n";
@@ -179,7 +179,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
- O << "$LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
+ O << "LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
<< CommentString << " " << I->getBasicBlock()->getName() << "\n";
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
@@ -190,7 +190,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
}
++LabelNumber;
- O << "\t.end\t" << CurrentFnName << "\n";
+ O << "\t.end " << CurrentFnName << "\n";
// We didn't modify anything.
return false;
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index 11299bd0aec..41028da7a25 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -447,19 +447,38 @@ void ISel::SelectBranchCC(SDOperand N)
//a = b: c = 0
//a < b: c < 0
//a > b: c > 0
- unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
- unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
- unsigned Tmp3 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::SUBT, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+
+ bool invTest = false;
+ unsigned Tmp3;
+
+ ConstantFPSDNode *CN;
+ if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
+ && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
+ Tmp3 = SelectExpr(SetCC->getOperand(0));
+ else if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
+ && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
+ {
+ Tmp3 = SelectExpr(SetCC->getOperand(1));
+ invTest = true;
+ }
+ else
+ {
+ unsigned Tmp1 = SelectExpr(SetCC->getOperand(0));
+ unsigned Tmp2 = SelectExpr(SetCC->getOperand(1));
+ bool isD = SetCC->getOperand(0).getValueType() == MVT::f64;
+ Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
+ BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
+ .addReg(Tmp1).addReg(Tmp2);
+ }
switch (SetCC->getCondition()) {
default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
- case ISD::SETEQ: Opc = Alpha::FBEQ; break;
- case ISD::SETLT: Opc = Alpha::FBLT; break;
- case ISD::SETLE: Opc = Alpha::FBLE; break;
- case ISD::SETGT: Opc = Alpha::FBGT; break;
- case ISD::SETGE: Opc = Alpha::FBGE; break;
- case ISD::SETNE: Opc = Alpha::FBNE; break;
+ case ISD::SETEQ: Opc = invTest ? Alpha::FBNE : Alpha::FBEQ; break;
+ case ISD::SETLT: Opc = invTest ? Alpha::FBGT : Alpha::FBLT; break;
+ case ISD::SETLE: Opc = invTest ? Alpha::FBGE : Alpha::FBLE; break;
+ case ISD::SETGT: Opc = invTest ? Alpha::FBLT : Alpha::FBGT; break;
+ case ISD::SETGE: Opc = invTest ? Alpha::FBLE : Alpha::FBGE; break;
+ case ISD::SETNE: Opc = invTest ? Alpha::FBEQ : Alpha::FBNE; break;
}
BuildMI(BB, Opc, 2).addReg(Tmp3).addMBB(Dest);
return;
@@ -598,9 +617,19 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
case ISD::SUB: Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS; break;
case ISD::SDIV: Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS; break;
};
- Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+
+ ConstantFPSDNode *CN;
+ if (opcode == ISD::SUB
+ && (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
+ && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
+ {
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
+ } else {
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ }
return Result;
case ISD::EXTLOAD:
@@ -1301,13 +1330,14 @@ unsigned ISel::SelectExpr(SDOperand N) {
// special calling conventions
//Restore GP because it is a call after all...
switch(opcode) {
- case ISD::UREM: AlphaLowering.restoreGP(BB); Opc = Alpha::REMQU; break;
- case ISD::SREM: AlphaLowering.restoreGP(BB); Opc = Alpha::REMQ; break;
- case ISD::UDIV: AlphaLowering.restoreGP(BB); Opc = Alpha::DIVQU; break;
- case ISD::SDIV: AlphaLowering.restoreGP(BB); Opc = Alpha::DIVQ; break;
+ case ISD::UREM: Opc = Alpha::REMQU; break;
+ case ISD::SREM: Opc = Alpha::REMQ; break;
+ case ISD::UDIV: Opc = Alpha::DIVQU; break;
+ case ISD::SDIV: Opc = Alpha::DIVQ; break;
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
+ AlphaLowering.restoreGP(BB);
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.td b/llvm/lib/Target/Alpha/AlphaInstrInfo.td
index 27ad8c07daf..fdf6a9a2e02 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.td
@@ -25,7 +25,7 @@ def s21imm : Operand<i32>;
def s64imm : Operand<i64>;
def PHI : PseudoInstAlpha<(ops ), "#phi">;
-def IDEF : PseudoInstAlpha<(ops ), "#idef">;
+def IDEF : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA">;
def WTF : PseudoInstAlpha<(ops ), "#wtf">;
def ADJUSTSTACKUP : PseudoInstAlpha<(ops ), "ADJUP">;
def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
@@ -337,18 +337,19 @@ def CPYSE : FPForm<0x17, 0x022, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpyse $RA,$
def CPYSN : FPForm<0x17, 0x021, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpysn $RA,$RB,$RC">; //Copy sign negate
//Basic Floating point ops
-def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds $RA,$RB,$RC">; //Add S_floating
-def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt $RA,$RB,$RC">; //Add T_floating
-def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs $RA,$RB,$RC">; //Subtract S_floating
-def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt $RA,$RB,$RC">; //Subtract T_floating
-def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs $RA,$RB,$RC">; //Divide S_floating
-def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt $RA,$RB,$RC">; //Divide T_floating
-def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls $RA,$RB,$RC">; //Multiply S_floating
-def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult $RA,$RB,$RC">; //Multiply T_floating
+def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds/sui $RA,$RB,$RC">; //Add S_floating
+def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt/sui $RA,$RB,$RC">; //Add T_floating
+def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs/sui $RA,$RB,$RC">; //Subtract S_floating
+def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt/sui $RA,$RB,$RC">; //Subtract T_floating
+def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs/sui $RA,$RB,$RC">; //Divide S_floating
+def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt/sui $RA,$RB,$RC">; //Divide T_floating
+def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls/sui $RA,$RB,$RC">; //Multiply S_floating
+def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult/sui $RA,$RB,$RC">; //Multiply T_floating
def SQRTS : FPForm<0x14, 0x08B, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrts $RA,$RB,$RC">; //Square root S_floating
def SQRTT : FPForm<0x14, 0x0AB, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrtt $RA,$RB,$RC">; //Square root T_floating
//INT reg to FP reg and back again
+//not supported on 21164
def FTOIS : FPForm<0x1C, 0x078, (ops FPRC:$RC, GPRC:$RA), "ftois $RA,$RC">; //Floating to integer move, S_floating
def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Floating to integer move, T_floating
def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating
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