2 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index bc5768e63a2..74781593a0d 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -128,7 +128,9 @@ protected:
   
   /// enablePostRAScheduler - True at 'More' optimization except
   /// for Thumb1.
-  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+                             TargetSubtarget::AntiDepBreakMode& mode) const {
+    mode = TargetSubtarget::ANTIDEP_NONE;
     return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
   }
 
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 27e43333f8c..0e4cfde7788 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -218,7 +218,9 @@ public:
 
   /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
   /// at 'More' optimization level.
-  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
+  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+                             TargetSubtarget::AntiDepBreakMode& mode) const {
+    mode = TargetSubtarget::ANTIDEP_NONE;
     return OptLevel >= CodeGenOpt::Default;
   }
 };