diff options
Diffstat (limited to 'llvm/lib/Target/XCore')
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreFrameLowering.cpp | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.cpp | 63 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.h | 32 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.h | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h | 15 |
8 files changed, 72 insertions, 98 deletions
diff --git a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp index 1d254a956eb..4c8c4446236 100644 --- a/llvm/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameLowering.cpp @@ -58,10 +58,9 @@ static bool CompareSSIOffset(const StackSlotInfo& a, const StackSlotInfo& b) { return a.Offset < b.Offset; } - static void EmitDefCfaRegister(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc dl, - const TargetInstrInfo &TII, + MachineBasicBlock::iterator MBBI, + const DebugLoc &dl, const TargetInstrInfo &TII, MachineModuleInfo *MMI, unsigned DRegNum) { unsigned CFIIndex = MMI->addFrameInst( MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum)); @@ -70,8 +69,8 @@ static void EmitDefCfaRegister(MachineBasicBlock &MBB, } static void EmitDefCfaOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc dl, - const TargetInstrInfo &TII, + MachineBasicBlock::iterator MBBI, + const DebugLoc &dl, const TargetInstrInfo &TII, MachineModuleInfo *MMI, int Offset) { unsigned CFIIndex = MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset)); @@ -80,7 +79,7 @@ static void EmitDefCfaOffset(MachineBasicBlock &MBB, } static void EmitCfiOffset(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc dl, + MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, MachineModuleInfo *MMI, unsigned DRegNum, int Offset) { unsigned CFIIndex = MMI->addFrameInst( @@ -96,7 +95,7 @@ static void EmitCfiOffset(MachineBasicBlock &MBB, /// \param OffsetFromTop the spill offset from the top of the frame. /// \param [in,out] Adjusted the current SP offset from the top of the frame. static void IfNeededExtSP(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc dl, + MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, MachineModuleInfo *MMI, int OffsetFromTop, int &Adjusted, int FrameSize, bool emitFrameMoves) { @@ -120,7 +119,7 @@ static void IfNeededExtSP(MachineBasicBlock &MBB, /// \param [in,out] RemainingAdj the current SP offset from the top of the /// frame. static void IfNeededLDAWSP(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, DebugLoc dl, + MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int OffsetFromTop, int &RemainingAdj) { while (OffsetFromTop < RemainingAdj - MaxImmU16) { @@ -187,10 +186,11 @@ getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, unsigned flags) { /// Restore clobbered registers with their spill slot value. /// The SP will be adjusted at the same time, thus the SpillList must be ordered /// with the largest (negative) offsets first. -static void -RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - DebugLoc dl, const TargetInstrInfo &TII, int &RemainingAdj, - SmallVectorImpl<StackSlotInfo> &SpillList) { +static void RestoreSpillList(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &dl, const TargetInstrInfo &TII, + int &RemainingAdj, + SmallVectorImpl<StackSlotInfo> &SpillList) { for (unsigned i = 0, e = SpillList.size(); i != e; ++i) { assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset"); assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset"); diff --git a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 8f49dcc6a6d..ce25cbcfd12 100644 --- a/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -46,7 +46,7 @@ namespace { /// getI32Imm - Return a target constant with the specified value, of type /// i32. - inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { + inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { return CurDAG->getTargetConstant(Imm, dl, MVT::i32); } diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index c42b2f63e9c..30097852666 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -368,10 +368,9 @@ LowerBR_JT(SDValue Op, SelectionDAG &DAG) const ScaledIndex); } -SDValue XCoreTargetLowering:: -lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base, - int64_t Offset, SelectionDAG &DAG) const -{ +SDValue XCoreTargetLowering::lowerLoadWordFromAlignedBasePlusOffset( + const SDLoc &DL, SDValue Chain, SDValue Base, int64_t Offset, + SelectionDAG &DAG) const { auto PtrVT = getPointerTy(DAG.getDataLayout()); if ((Offset & 0x3) == 0) { return DAG.getLoad(PtrVT, DL, Chain, Base, MachinePointerInfo(), false, @@ -1068,11 +1067,10 @@ XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, /// LowerCallResult - Lower the result values of a call into the /// appropriate copies out of appropriate physical registers / memory locations. -static SDValue -LowerCallResult(SDValue Chain, SDValue InFlag, - const SmallVectorImpl<CCValAssign> &RVLocs, - SDLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) { +static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, + const SmallVectorImpl<CCValAssign> &RVLocs, + const SDLoc &dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) { SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs; // Copy results out of physical registers. for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { @@ -1115,15 +1113,12 @@ LowerCallResult(SDValue Chain, SDValue InFlag, /// regs to (physical regs)/(stack frame), CALLSEQ_START and /// CALLSEQ_END are emitted. /// TODO: isTailCall, sret. -SDValue -XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, - CallingConv::ID CallConv, bool isVarArg, - bool isTailCall, - const SmallVectorImpl<ISD::OutputArg> &Outs, - const SmallVectorImpl<SDValue> &OutVals, - const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) const { +SDValue XCoreTargetLowering::LowerCCCCallTo( + SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, + bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { // Analyze operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; @@ -1253,15 +1248,10 @@ namespace { } /// XCore formal arguments implementation -SDValue -XCoreTargetLowering::LowerFormalArguments(SDValue Chain, - CallingConv::ID CallConv, - bool isVarArg, - const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc dl, - SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) - const { +SDValue XCoreTargetLowering::LowerFormalArguments( + SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { switch (CallConv) { default: @@ -1277,15 +1267,10 @@ XCoreTargetLowering::LowerFormalArguments(SDValue Chain, /// virtual registers and generate load operations for /// arguments places on the stack. /// TODO: sret -SDValue -XCoreTargetLowering::LowerCCCArguments(SDValue Chain, - CallingConv::ID CallConv, - bool isVarArg, - const SmallVectorImpl<ISD::InputArg> - &Ins, - SDLoc dl, - SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) const { +SDValue XCoreTargetLowering::LowerCCCArguments( + SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); @@ -1460,11 +1445,11 @@ CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, } SDValue -XCoreTargetLowering::LowerReturn(SDValue Chain, - CallingConv::ID CallConv, bool isVarArg, +XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, + bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, - SDLoc dl, SelectionDAG &DAG) const { + const SDLoc &dl, SelectionDAG &DAG) const { XCoreFunctionInfo *XFI = DAG.getMachineFunction().getInfo<XCoreFunctionInfo>(); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h index 287a77e2653..abd8a688b30 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.h +++ b/llvm/lib/Target/XCore/XCoreISelLowering.h @@ -144,11 +144,10 @@ namespace llvm { const XCoreSubtarget &Subtarget; // Lower Operand helpers - SDValue LowerCCCArguments(SDValue Chain, - CallingConv::ID CallConv, + SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc dl, SelectionDAG &DAG, + const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, @@ -156,13 +155,14 @@ namespace llvm { const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc dl, SelectionDAG &DAG, + const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, SelectionDAG &DAG) const; - SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, - SDValue Base, int64_t Offset, + SDValue lowerLoadWordFromAlignedBasePlusOffset(const SDLoc &DL, + SDValue Chain, SDValue Base, + int64_t Offset, SelectionDAG &DAG) const; // Lower Operand specifics @@ -206,23 +206,19 @@ namespace llvm { unsigned Depth = 0) const override; SDValue - LowerFormalArguments(SDValue Chain, - CallingConv::ID CallConv, - bool isVarArg, - const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) const override; + LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, + const SDLoc &dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const override; SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const override; - SDValue - LowerReturn(SDValue Chain, - CallingConv::ID CallConv, bool isVarArg, - const SmallVectorImpl<ISD::OutputArg> &Outs, - const SmallVectorImpl<SDValue> &OutVals, - SDLoc dl, SelectionDAG &DAG) const override; + SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SDLoc &dl, SelectionDAG &DAG) const override; bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index 4063abcb02a..19b74632609 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -272,11 +272,11 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, return true; } -unsigned -XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - ArrayRef<MachineOperand> Cond, - DebugLoc DL)const{ +unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef<MachineOperand> Cond, + const DebugLoc &DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -329,9 +329,9 @@ XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { } void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const { + MachineBasicBlock::iterator I, + const DebugLoc &DL, unsigned DestReg, + unsigned SrcReg, bool KillSrc) const { bool GRDest = XCore::GRRegsRegClass.contains(DestReg); bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index b958c361f5a..69e75c586fe 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -57,13 +57,12 @@ public: unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, - DebugLoc DL) const override; + const DebugLoc &DL) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; - void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, + void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp index 40568d124de..457672e80ab 100644 --- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp @@ -16,13 +16,10 @@ using namespace llvm; #define DEBUG_TYPE "xcore-selectiondag-info" -SDValue XCoreSelectionDAGInfo:: -EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, - SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool isVolatile, bool AlwaysInline, - MachinePointerInfo DstPtrInfo, - MachinePointerInfo SrcPtrInfo) const -{ +SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy( + SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, + MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { unsigned SizeBitWidth = Size.getValueType().getSizeInBits(); // Call __memcpy_4 if the src, dst and size are all 4 byte aligned. if (!AlwaysInline && (Align & 3) == 0 && diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h index 456688568f4..7cd0d8216e9 100644 --- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h +++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h @@ -22,15 +22,12 @@ class XCoreTargetMachine; class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo { public: - - SDValue - EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, - SDValue Chain, - SDValue Op1, SDValue Op2, - SDValue Op3, unsigned Align, bool isVolatile, - bool AlwaysInline, - MachinePointerInfo DstPtrInfo, - MachinePointerInfo SrcPtrInfo) const override; + SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, + SDValue Chain, SDValue Op1, SDValue Op2, + SDValue Op3, unsigned Align, bool isVolatile, + bool AlwaysInline, + MachinePointerInfo DstPtrInfo, + MachinePointerInfo SrcPtrInfo) const override; }; } |
