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-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td6
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td6
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td6
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td6
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td6
5 files changed, 10 insertions, 20 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index d78a3581849..ac6c232486e 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -455,6 +455,7 @@ def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
+def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
"ADC(16|32|64)i",
"ADC(8|16|32|64)rr",
@@ -468,9 +469,7 @@ def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "CDQ",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
- "CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
@@ -605,14 +604,13 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
+def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
- "CBW",
"CLC",
"CMC",
"CMP(8|16|32|64)ri",
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 19064eff750..96f02546948 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -813,6 +813,7 @@ def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
+def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
@@ -821,8 +822,6 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "CDQ",
- "CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
@@ -954,14 +953,13 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup10], (instrs CWDE)>;
+def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
- "CBW",
"CLC",
"CMC",
"CMP(8|16|32|64)ri",
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 67a4f5881e0..827e727b077 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -369,6 +369,7 @@ def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
+def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
@@ -377,8 +378,6 @@ def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "CDQ",
- "CQO",
"LAHF",
"SAHF",
"SAR(8|16|32|64)ri",
@@ -488,14 +487,13 @@ def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup6], (instrs CWDE)>;
+def: InstRW<[SBWriteResGroup6], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
- "CBW",
"CMC",
"CMP(8|16|32|64)ri",
"CMP(8|16|32|64)rr",
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index a3225d39f8a..255eea9edbf 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -519,6 +519,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
+def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO)>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
"ADC(16|32|64)i",
"ADC(8|16|32|64)rr",
@@ -532,10 +533,8 @@ def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "CDQ",
"CLAC",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
- "CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
@@ -609,14 +608,13 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>;
+def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
- "CBW",
"CLC",
"CMC",
"CMP(8|16|32|64)ri",
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 2488467a6ce..1b41759ee69 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -995,6 +995,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
+def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO)>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
"ADC(16|32|64)i",
"ADC(8|16|32|64)rr",
@@ -1008,10 +1009,8 @@ def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "CDQ",
"CLAC",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
- "CQO",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
"J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
"JMP_1",
@@ -1269,14 +1268,13 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup10], (instrs CWDE)>;
+def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri",
"ADD(8|16|32|64)rr",
"ADD(8|16|32|64)i",
"AND(8|16|32|64)ri",
"AND(8|16|32|64)rr",
"AND(8|16|32|64)i",
- "CBW",
"CLC",
"CMC",
"CMP(8|16|32|64)ri",
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