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-rw-r--r--llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp10
-rw-r--r--llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp4
-rw-r--r--llvm/lib/Target/X86/AsmParser/X86Operand.h32
-rw-r--r--llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp66
-rw-r--r--llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp2
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.cpp2
-rw-r--r--llvm/lib/Target/X86/X86MCInstLower.cpp49
7 files changed, 82 insertions, 83 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
index 85ab2ef58f4..5d977b22280 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
@@ -245,7 +245,7 @@ protected:
assert(VT == MVT::i32 || VT == MVT::i64);
MCInst Inst;
Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
- Inst.addOperand(MCOperand::CreateReg(getX86SubSuperRegister(Reg, VT)));
+ Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, VT)));
Op.addMemOperands(Inst, 5);
EmitInstruction(Out, Inst);
}
@@ -642,7 +642,7 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
{
MCInst Inst;
Inst.setOpcode(X86::MOV8rm);
- Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
+ Inst.addOperand(MCOperand::createReg(ShadowRegI8));
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op(
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
@@ -725,7 +725,7 @@ void X86AddressSanitizer32::InstrumentMemOperandLarge(
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
SMLoc(), SMLoc()));
Op->addMemOperands(Inst, 5);
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
EmitInstruction(Out, Inst);
}
MCSymbol *DoneSym = Ctx.CreateTempSymbol();
@@ -913,7 +913,7 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
{
MCInst Inst;
Inst.setOpcode(X86::MOV8rm);
- Inst.addOperand(MCOperand::CreateReg(ShadowRegI8));
+ Inst.addOperand(MCOperand::createReg(ShadowRegI8));
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
std::unique_ptr<X86Operand> Op(
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
@@ -996,7 +996,7 @@ void X86AddressSanitizer64::InstrumentMemOperandLarge(
X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
SMLoc(), SMLoc()));
Op->addMemOperands(Inst, 5);
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
EmitInstruction(Out, Inst);
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 244a94e9aa7..605c697e47b 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -2333,8 +2333,8 @@ static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
if (!isCmp)
- TmpInst.addOperand(MCOperand::CreateReg(Reg));
- TmpInst.addOperand(MCOperand::CreateReg(Reg));
+ TmpInst.addOperand(MCOperand::createReg(Reg));
+ TmpInst.addOperand(MCOperand::createReg(Reg));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h
index 94dbedb4c8a..f5a1b3c528d 100644
--- a/llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -357,14 +357,14 @@ struct X86Operand : public MCParsedAsmOperand {
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
static unsigned getGR32FromGR64(unsigned RegNo) {
@@ -395,7 +395,7 @@ struct X86Operand : public MCParsedAsmOperand {
unsigned RegNo = getReg();
if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
RegNo = getGR32FromGR64(RegNo);
- Inst.addOperand(MCOperand::CreateReg(RegNo));
+ Inst.addOperand(MCOperand::createReg(RegNo));
}
void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
@@ -408,40 +408,40 @@ struct X86Operand : public MCParsedAsmOperand {
void addMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 5) && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
- Inst.addOperand(MCOperand::CreateImm(getMemScale()));
- Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
+ Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
+ Inst.addOperand(MCOperand::createImm(getMemScale()));
+ Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
addExpr(Inst, getMemDisp());
- Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
+ Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}
void addAbsMemOperands(MCInst &Inst, unsigned N) const {
assert((N == 1) && "Invalid number of operands!");
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
+ Inst.addOperand(MCOperand::createExpr(getMemDisp()));
}
void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
assert((N == 2) && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
- Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
+ Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
+ Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}
void addDstIdxOperands(MCInst &Inst, unsigned N) const {
assert((N == 1) && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
+ Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
}
void addMemOffsOperands(MCInst &Inst, unsigned N) const {
assert((N == 2) && "Invalid number of operands!");
// Add as immediates when possible.
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
- Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
+ Inst.addOperand(MCOperand::createExpr(getMemDisp()));
+ Inst.addOperand(MCOperand::createReg(getMemSegReg()));
}
static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index e8c547517b0..772294cc360 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -180,7 +180,7 @@ static void translateRegister(MCInst &mcInst, Reg reg) {
#undef ENTRY
uint8_t llvmRegnum = llvmRegnums[reg];
- mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
+ mcInst.addOperand(MCOperand::createReg(llvmRegnum));
}
/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
@@ -248,11 +248,11 @@ static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
assert(insn.mode == MODE_16BIT);
baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
}
- MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
+ MCOperand baseReg = MCOperand::createReg(baseRegNo);
mcInst.addOperand(baseReg);
MCOperand segmentReg;
- segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
+ segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
mcInst.addOperand(segmentReg);
return false;
}
@@ -273,7 +273,7 @@ static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
assert(insn.mode == MODE_16BIT);
baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
}
- MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
+ MCOperand baseReg = MCOperand::createReg(baseRegNo);
mcInst.addOperand(baseReg);
return false;
}
@@ -539,13 +539,13 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate,
case TYPE_XMM32:
case TYPE_XMM64:
case TYPE_XMM128:
- mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
+ mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
return;
case TYPE_XMM256:
- mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
+ mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
return;
case TYPE_XMM512:
- mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
+ mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
return;
case TYPE_REL8:
isBranch = true;
@@ -568,12 +568,12 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate,
if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
insn.immediateOffset, insn.immediateSize,
mcInst, Dis))
- mcInst.addOperand(MCOperand::CreateImm(immediate));
+ mcInst.addOperand(MCOperand::createImm(immediate));
if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
MCOperand segmentReg;
- segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
+ segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
mcInst.addOperand(segmentReg);
}
}
@@ -606,7 +606,7 @@ static bool translateRMRegister(MCInst &mcInst,
return true;
#define ENTRY(x) \
case EA_REG_##x: \
- mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
+ mcInst.addOperand(MCOperand::createReg(X86::x)); break;
ALL_REGS
#undef ENTRY
}
@@ -651,12 +651,12 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
return true;
#define ENTRY(x) \
case SIB_BASE_##x: \
- baseReg = MCOperand::CreateReg(X86::x); break;
+ baseReg = MCOperand::createReg(X86::x); break;
ALL_SIB_BASES
#undef ENTRY
}
} else {
- baseReg = MCOperand::CreateReg(0);
+ baseReg = MCOperand::createReg(0);
}
// Check whether we are handling VSIB addressing mode for GATHER.
@@ -706,7 +706,7 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
return true;
#define ENTRY(x) \
case SIB_INDEX_##x: \
- indexReg = MCOperand::CreateReg(X86::x); break;
+ indexReg = MCOperand::createReg(X86::x); break;
EA_BASES_32BIT
EA_BASES_64BIT
REGS_XMM
@@ -715,10 +715,10 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
#undef ENTRY
}
} else {
- indexReg = MCOperand::CreateReg(0);
+ indexReg = MCOperand::createReg(0);
}
- scaleAmount = MCOperand::CreateImm(insn.sibScale);
+ scaleAmount = MCOperand::createImm(insn.sibScale);
} else {
switch (insn.eaBase) {
case EA_BASE_NONE:
@@ -732,31 +732,31 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
tryAddingPcLoadReferenceComment(insn.startLocation +
insn.displacementOffset,
insn.displacement + pcrel, Dis);
- baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
+ baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6
}
else
- baseReg = MCOperand::CreateReg(0);
+ baseReg = MCOperand::createReg(0);
- indexReg = MCOperand::CreateReg(0);
+ indexReg = MCOperand::createReg(0);
break;
case EA_BASE_BX_SI:
- baseReg = MCOperand::CreateReg(X86::BX);
- indexReg = MCOperand::CreateReg(X86::SI);
+ baseReg = MCOperand::createReg(X86::BX);
+ indexReg = MCOperand::createReg(X86::SI);
break;
case EA_BASE_BX_DI:
- baseReg = MCOperand::CreateReg(X86::BX);
- indexReg = MCOperand::CreateReg(X86::DI);
+ baseReg = MCOperand::createReg(X86::BX);
+ indexReg = MCOperand::createReg(X86::DI);
break;
case EA_BASE_BP_SI:
- baseReg = MCOperand::CreateReg(X86::BP);
- indexReg = MCOperand::CreateReg(X86::SI);
+ baseReg = MCOperand::createReg(X86::BP);
+ indexReg = MCOperand::createReg(X86::SI);
break;
case EA_BASE_BP_DI:
- baseReg = MCOperand::CreateReg(X86::BP);
- indexReg = MCOperand::CreateReg(X86::DI);
+ baseReg = MCOperand::createReg(X86::BP);
+ indexReg = MCOperand::createReg(X86::DI);
break;
default:
- indexReg = MCOperand::CreateReg(0);
+ indexReg = MCOperand::createReg(0);
switch (insn.eaBase) {
default:
debug("Unexpected eaBase");
@@ -767,7 +767,7 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
// placeholders to keep the compiler happy.
#define ENTRY(x) \
case EA_BASE_##x: \
- baseReg = MCOperand::CreateReg(X86::x); break;
+ baseReg = MCOperand::createReg(X86::x); break;
ALL_EA_BASES
#undef ENTRY
#define ENTRY(x) case EA_REG_##x:
@@ -779,12 +779,12 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
}
}
- scaleAmount = MCOperand::CreateImm(1);
+ scaleAmount = MCOperand::createImm(1);
}
- displacement = MCOperand::CreateImm(insn.displacement);
+ displacement = MCOperand::createImm(insn.displacement);
- segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
+ segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]);
mcInst.addOperand(baseReg);
mcInst.addOperand(scaleAmount);
@@ -856,7 +856,7 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
/// @param stackPos - The stack position to translate.
static void translateFPRegister(MCInst &mcInst,
uint8_t stackPos) {
- mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
+ mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
}
/// translateMaskRegister - Translates a 3-bit mask register number to
@@ -872,7 +872,7 @@ static bool translateMaskRegister(MCInst &mcInst,
return true;
}
- mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
+ mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
return false;
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index e27b7cb5946..386d9f32b96 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1475,7 +1475,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
RegNum |= Val;
}
}
- EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
+ EmitImmediate(MCOperand::createImm(RegNum), MI.getLoc(), 1, FK_Data_1,
CurByte, OS, Fixups);
} else {
EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index dba9fec139a..36504d21910 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -6113,7 +6113,7 @@ void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
void X86InstrInfo::getUnconditionalBranch(
MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Branch.setOpcode(X86::JMP_1);
- Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
+ Branch.addOperand(MCOperand::createExpr(BranchTarget));
}
// This code must remain in sync with getJumpInstrTableEntryBound in this class!
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index d55e9f656b0..fb3afc0b088 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -288,7 +288,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
Expr = MCBinaryExpr::CreateAdd(Expr,
MCConstantExpr::Create(MO.getOffset(), Ctx),
Ctx);
- return MCOperand::CreateExpr(Expr);
+ return MCOperand::createExpr(Expr);
}
@@ -412,10 +412,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
- MCOp = MCOperand::CreateReg(MO.getReg());
+ MCOp = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
+ MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
@@ -714,28 +714,28 @@ void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
MCInst LEA;
if (is64Bits) {
LEA.setOpcode(X86::LEA64r);
- LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
- LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
- LEA.addOperand(MCOperand::CreateImm(1)); // scale
- LEA.addOperand(MCOperand::CreateReg(0)); // index
- LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
- LEA.addOperand(MCOperand::CreateReg(0)); // seg
+ LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
+ LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
+ LEA.addOperand(MCOperand::createImm(1)); // scale
+ LEA.addOperand(MCOperand::createReg(0)); // index
+ LEA.addOperand(MCOperand::createExpr(symRef)); // disp
+ LEA.addOperand(MCOperand::createReg(0)); // seg
} else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
LEA.setOpcode(X86::LEA32r);
- LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
- LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
- LEA.addOperand(MCOperand::CreateImm(1)); // scale
- LEA.addOperand(MCOperand::CreateReg(0)); // index
- LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
- LEA.addOperand(MCOperand::CreateReg(0)); // seg
+ LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
+ LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
+ LEA.addOperand(MCOperand::createImm(1)); // scale
+ LEA.addOperand(MCOperand::createReg(0)); // index
+ LEA.addOperand(MCOperand::createExpr(symRef)); // disp
+ LEA.addOperand(MCOperand::createReg(0)); // seg
} else {
LEA.setOpcode(X86::LEA32r);
- LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
- LEA.addOperand(MCOperand::CreateReg(0)); // base
- LEA.addOperand(MCOperand::CreateImm(1)); // scale
- LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
- LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
- LEA.addOperand(MCOperand::CreateReg(0)); // seg
+ LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
+ LEA.addOperand(MCOperand::createReg(0)); // base
+ LEA.addOperand(MCOperand::createImm(1)); // scale
+ LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
+ LEA.addOperand(MCOperand::createExpr(symRef)); // disp
+ LEA.addOperand(MCOperand::createReg(0)); // seg
}
EmitAndCountInstruction(LEA);
@@ -813,7 +813,6 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
StatepointOpers SOpers(&MI);
-
if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
getSubtargetInfo());
@@ -834,7 +833,7 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
// symbol is to far away. (TODO: support non-relative addressing)
break;
case MachineOperand::MO_Immediate:
- CallTargetMCOp = MCOperand::CreateImm(CallTarget.getImm());
+ CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
CallOpcode = X86::CALL64pcrel32;
// Currently, we only support relative addressing with statepoints.
// Otherwise, we'll need a scratch register to hold the target
@@ -842,7 +841,7 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
// address is to far away. (TODO: support non-relative addressing)
break;
case MachineOperand::MO_Register:
- CallTargetMCOp = MCOperand::CreateReg(CallTarget.getReg());
+ CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
CallOpcode = X86::CALL64r;
break;
default:
@@ -898,7 +897,7 @@ void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
llvm_unreachable("Unrecognized callee operand type.");
case MachineOperand::MO_Immediate:
if (CalleeMO.getImm())
- CalleeMCOp = MCOperand::CreateImm(CalleeMO.getImm());
+ CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
break;
case MachineOperand::MO_ExternalSymbol:
case MachineOperand::MO_GlobalAddress:
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