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-rw-r--r--llvm/lib/Target/X86/X86ATTAsmPrinter.cpp6
-rw-r--r--llvm/lib/Target/X86/X86CodeEmitter.cpp8
-rw-r--r--llvm/lib/Target/X86/X86Instr64bit.td5
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.td11
-rw-r--r--llvm/lib/Target/X86/X86InstrMMX.td13
-rw-r--r--llvm/lib/Target/X86/X86InstrSSE.td25
-rw-r--r--llvm/lib/Target/X86/X86IntelAsmPrinter.cpp6
7 files changed, 4 insertions, 70 deletions
diff --git a/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp b/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
index e51e065540e..ea003c33193 100644
--- a/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -205,7 +205,6 @@ static inline bool printStub(TargetMachine &TM, const X86Subtarget* ST) {
void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier, bool NotRIPRel) {
const MachineOperand &MO = MI->getOperand(OpNo);
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@@ -218,7 +217,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
+ for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
O << (char)tolower(*Name);
return;
}
@@ -548,7 +547,6 @@ void X86ATTAsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI,
bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
@@ -570,7 +568,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
}
O << '%';
- for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
+ for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
O << (char)tolower(*Name);
return false;
}
diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index 33b87be50d2..87481c7d7f1 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -623,14 +623,6 @@ void Emitter::emitInstruction(const MachineInstr &MI,
break;
case TargetInstrInfo::DECLARE:
case X86::DWARF_LOC:
- case X86::IMPLICIT_DEF_GR8:
- case X86::IMPLICIT_DEF_GR16:
- case X86::IMPLICIT_DEF_GR32:
- case X86::IMPLICIT_DEF_GR64:
- case X86::IMPLICIT_DEF_FR32:
- case X86::IMPLICIT_DEF_FR64:
- case X86::IMPLICIT_DEF_VR64:
- case X86::IMPLICIT_DEF_VR128:
case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td
index f3c873e4db2..730f3930bf4 100644
--- a/llvm/lib/Target/X86/X86Instr64bit.td
+++ b/llvm/lib/Target/X86/X86Instr64bit.td
@@ -86,11 +86,6 @@ def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
// Instruction list...
//
-let isImplicitDef = 1 in
-def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR64:$dst, (undef))]>;
-
//===----------------------------------------------------------------------===//
// Call Instructions...
//
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index e32fb9c4b53..9c034644f1a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -279,17 +279,6 @@ def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
"#ADJCALLSTACKUP",
[(X86callseq_end imm:$amt1, imm:$amt2)]>;
}
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR8:$dst, (undef))]>;
-def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR16:$dst, (undef))]>;
-def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set GR32:$dst, (undef))]>;
-}
// Nop
let neverHasSideEffects = 1 in
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td
index 0a18fa53f1e..3d8bd1f579c 100644
--- a/llvm/lib/Target/X86/X86InstrMMX.td
+++ b/llvm/lib/Target/X86/X86InstrMMX.td
@@ -13,19 +13,6 @@
//
//===----------------------------------------------------------------------===//
-// Some 'special' instructions
-let isImplicitDef = 1 in
-def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set VR64:$dst, (v8i8 (undef)))]>,
- Requires<[HasMMX]>;
-
-// 64-bit vector undef's.
-def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
-def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
-def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
-def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
-
//===----------------------------------------------------------------------===//
// MMX Pattern Fragments
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 9b632e472ba..ff19dc02cc2 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -49,23 +49,6 @@ def X86insrtps : SDNode<"X86ISD::INSERTPS",
SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
//===----------------------------------------------------------------------===//
-// SSE 'Special' Instructions
-//===----------------------------------------------------------------------===//
-
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set VR128:$dst, (v4f32 (undef)))]>,
- Requires<[HasSSE1]>;
-def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
-def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
- "#IMPLICIT_DEF $dst",
- [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
-}
-
-//===----------------------------------------------------------------------===//
// SSE Complex Patterns
//===----------------------------------------------------------------------===//
@@ -2754,14 +2737,6 @@ let Constraints = "$src1 = $dst" in {
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
-// 128-bit vector undef's.
-def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
-
// extload f32 -> f64. This matches load+fextend because we have a hack in
// the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
// Since these loads aren't folded into the fextend, we have to match it
diff --git a/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp b/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
index 16d819a3d7c..0caab87dd03 100644
--- a/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -114,7 +114,6 @@ void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register: {
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
@@ -125,7 +124,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- O << RI.get(Reg).AsmName;
+ O << TRI->getAsmName(Reg);
} else
O << "reg" << MO.getReg();
return;
@@ -253,7 +252,6 @@ void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
const char Mode) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; // Unknown mode.
@@ -271,7 +269,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
break;
}
- O << '%' << RI.get(Reg).AsmName;
+ O << '%' << TRI->getAsmName(Reg);
return false;
}
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