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-rw-r--r--llvm/lib/Target/X86/X86Subtarget.cpp12
1 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index df1f7db85fc..d54ccb37e3b 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -74,8 +74,8 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
/// cases where GVRequiresExtraLoad is true. Some variations of PIC require
/// a register, but not an extra load.
bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
- const TargetMachine& TM,
- bool isDirectCall) const
+ const TargetMachine& TM,
+ bool isDirectCall) const
{
if (GVRequiresExtraLoad(GV, TM, isDirectCall))
return true;
@@ -99,6 +99,14 @@ const char *X86Subtarget::getBZeroEntry() const {
return 0;
}
+/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
+/// to immediate address.
+bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
+ if (Is64Bit)
+ return false;
+ return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
+}
+
/// getSpecialAddressLatency - For targets where it is beneficial to
/// backschedule instructions that compute addresses, return a value
/// indicating the number of scheduling cycles of backscheduling that
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