diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedHaswell.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index b9f9c8c485a..52fc47398e2 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -726,16 +726,12 @@ def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8", "BTR(16|32|64)rr", "BTS(16|32|64)ri8", "BTS(16|32|64)rr", - "RORX(32|64)ri", "SAR(8|16|32|64)r1", "SAR(8|16|32|64)ri", - "SARX(32|64)rr", "SHL(8|16|32|64)r1", "SHL(8|16|32|64)ri", - "SHLX(32|64)rr", "SHR(8|16|32|64)r1", - "SHR(8|16|32|64)ri", - "SHRX(32|64)rr")>; + "SHR(8|16|32|64)ri")>; def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { let Latency = 1; @@ -956,11 +952,7 @@ def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8", - "RORX(32|64)mi", - "SARX(32|64)rm", - "SHLX(32|64)rm", - "SHRX(32|64)rm")>; +def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>; def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { let Latency = 6; |
