diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a0fd3d90c5e..38949601f6a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1207,13 +1207,25 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { RC = X86::FR32RegisterClass; else if (RegVT == MVT::f64) RC = X86::FR64RegisterClass; - else { - assert(MVT::isVector(RegVT)); - if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) { - RC = X86::GR64RegisterClass; // MMX values are passed in GPRs. - RegVT = MVT::i64; - } else - RC = X86::VR128RegisterClass; + else if (MVT::isVector(RegVT) && MVT::getSizeInBits(RegVT) == 128) + RC = X86::VR128RegisterClass; + else if (MVT::isVector(RegVT)) { + assert(MVT::getSizeInBits(RegVT) == 64); + if (!Is64Bit) + RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. + else { + // Darwin calling convention passes MMX values in either GPRs or + // XMMs in x86-64. Other targets pass them in memory. + if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { + RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. + RegVT = MVT::v2i64; + } else { + RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. + RegVT = MVT::i64; + } + } + } else { + assert(0 && "Unknown argument type!"); } unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); |
