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-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7ee8bbc6828..7135be37ffc 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -14568,6 +14568,13 @@ static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
}
+ // Canonicalize result type to MVT::i32.
+ if (EltVT != MVT::i32) {
+ SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ Vec, Idx);
+ return DAG.getAnyExtOrTrunc(Extract, dl, EltVT);
+ }
+
// If the kshift instructions of the correct width aren't natively supported
// then we need to promote the vector to the native size to get the correct
// zeroing behavior.
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