diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fb871266546..e258e65f165 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18214,24 +18214,6 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, if (VTOp0 == MVT::v2i32) return SDValue(); - if (VT.is128BitVector() && VTOp0.is256BitVector()) { - // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type - // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the - // legalizer firstly checks if the first operand in input to the setcc has - // a legal type. If so, then it promotes the return type to that same type. - // Otherwise, the return type is promoted to the 'next legal type' which, - // for a vector of MVT::i1 is always a 128-bit integer vector type. - // - // We reach this code only if the following two conditions are met: - // 1. Both return type and operand type have been promoted to wider types - // by the type legalizer. - // 2. The original operand type has been promoted to a 256-bit vector. - // - // Note that condition 2. only applies for AVX targets. - SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, Cond); - return DAG.getZExtOrTrunc(NewOp, dl, VT); - } - // The non-AVX512 code below works under the assumption that source and // destination types are the same. assert((Subtarget.hasAVX512() || (VT == VTOp0)) && |
