diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86FixupLEAs.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86FixupLEAs.cpp | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index 157b07d819b..d85389a0a7f 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -286,6 +286,8 @@ static inline bool isRegOperand(const MachineOperand &Op) { } /// hasIneffecientLEARegs - LEA that uses base and index registers /// where the base is EBP, RBP, or R13 +// TODO: use a variant scheduling class to model the latency profile +// of LEA instructions, and implement this logic as a scheduling predicate. static inline bool hasInefficientLEABaseReg(const MachineOperand &Base, const MachineOperand &Index) { return Base.isReg() && isInefficientLEAReg(Base.getReg()) && @@ -296,13 +298,6 @@ static inline bool hasLEAOffset(const MachineOperand &Offset) { return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal(); } -// LEA instruction that has all three operands: offset, base and index -static inline bool isThreeOperandsLEA(const MachineOperand &Base, - const MachineOperand &Index, - const MachineOperand &Offset) { - return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset); -} - static inline int getADDrrFromLEA(int LEAOpcode) { switch (LEAOpcode) { default: @@ -477,7 +472,7 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, const MachineOperand &Offset = MI.getOperand(4); const MachineOperand &Segment = MI.getOperand(5); - if (!(isThreeOperandsLEA(Base, Index, Offset) || + if (!(TII->isThreeOperandsLEA(MI) || hasInefficientLEABaseReg(Base, Index)) || !TII->isSafeToClobberEFLAGS(*MFI, MI) || Segment.getReg() != X86::NoRegister) |
