diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 233 |
1 files changed, 95 insertions, 138 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 06b8b466674..d324e53ea14 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -125,6 +125,9 @@ def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", "Enable AVX-512 PreFetch Instructions", [FeatureAVX512]>; +def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPFPREFETCHWT1", + "true", + "Prefetch with Intent to Write and T1 Hint">; def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", "Enable AVX-512 Doubleword and Quadword Instructions", [FeatureAVX512]>; @@ -137,6 +140,9 @@ def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", "Enable AVX-512 Vector Bit Manipulation Instructions", [FeatureAVX512]>; +def FeatureIFMA : SubtargetFeature<"ifma", "HasIFMA", "true", + "Enable AVX-512 Integer Fused Multiple-Add", + [FeatureAVX512]>; def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", "Enable protection keys">; def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", @@ -202,6 +208,20 @@ def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw", def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", "PadShortFunctions", "true", "Pad short functions">; +def FeatureINVPCID : SubtargetFeature<"invpcid", "HasInvPCId", "true", + "Invalidate Process-Context Identifier">; +def FeatureVMFUNC : SubtargetFeature<"vmfunc", "HasVMFUNC", "true", + "VM Functions">; +def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true", + "Supervisor Mode Access Protection">; +def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", + "Enable Software Guard Extensions">; +def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", + "Flush A Cache Line Optimized">; +def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true", + "Enable Persistent Commit">; +def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", + "Cache Line Write Back">; // TODO: This feature ought to be renamed. // What it really refers to are CPUs for which certain instructions // (which ones besides the example below?) are microcoded. @@ -365,13 +385,12 @@ def : WestmereProc<"westmere">; // SSE is not listed here since llvm treats AVX as a reimplementation of SSE, // rather than a superset. -class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ +def ProcIntelSNB : SubtargetFeature<"snb", "X86ProcFamily", "IntelSNB", + " Intel SandyBridge Processor", [ FeatureMMX, FeatureAVX, FeatureFXSR, FeatureCMPXCHG16B, - FeatureSlowBTMem, - FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES, FeaturePCLMUL, @@ -379,187 +398,125 @@ class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ FeatureXSAVEOPT, FeatureLAHFSAHF ]>; + +class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ + ProcIntelSNB, + FeatureSlowBTMem, + FeatureSlowUAMem32 +]>; def : SandyBridgeProc<"sandybridge">; def : SandyBridgeProc<"corei7-avx">; // Legacy alias. -class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ - FeatureMMX, - FeatureAVX, - FeatureFXSR, - FeatureCMPXCHG16B, - FeatureSlowBTMem, - FeatureSlowUAMem32, - FeaturePOPCNT, - FeatureAES, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, +def ProcIntelIVB : SubtargetFeature<"ivb", "X86ProcFamily", "IntelIVB", + " Intel IvyBridge Processor", [ + ProcIntelSNB, FeatureRDRAND, FeatureF16C, - FeatureFSGSBase, - FeatureLAHFSAHF + FeatureFSGSBase +]>; + +class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [ + ProcIntelIVB, + FeatureSlowBTMem, + FeatureSlowUAMem32 ]>; def : IvyBridgeProc<"ivybridge">; def : IvyBridgeProc<"core-avx-i">; // Legacy alias. -class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [ - FeatureMMX, +def ProcIntelHSW : SubtargetFeature<"hsw", "X86ProcFamily", "IntelHSW", + " Intel Haswell Processor", [ + ProcIntelIVB, FeatureAVX2, - FeatureFXSR, - FeatureCMPXCHG16B, - FeatureSlowBTMem, - FeaturePOPCNT, - FeatureAES, - FeaturePCLMUL, - FeatureRDRAND, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureF16C, - FeatureFSGSBase, - FeatureMOVBE, - FeatureLZCNT, FeatureBMI, FeatureBMI2, FeatureFMA, + FeatureLZCNT, + FeatureMOVBE, + FeatureINVPCID, + FeatureVMFUNC, FeatureRTM, FeatureHLE, - FeatureSlowIncDec, - FeatureLAHFSAHF + FeatureSlowIncDec ]>; + +class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, + [ProcIntelHSW]>; def : HaswellProc<"haswell">; def : HaswellProc<"core-avx2">; // Legacy alias. -class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [ - FeatureMMX, - FeatureAVX2, - FeatureFXSR, - FeatureCMPXCHG16B, - FeatureSlowBTMem, - FeaturePOPCNT, - FeatureAES, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureRDRAND, - FeatureF16C, - FeatureFSGSBase, - FeatureMOVBE, - FeatureLZCNT, - FeatureBMI, - FeatureBMI2, - FeatureFMA, - FeatureRTM, - FeatureHLE, +def ProcIntelBDW : SubtargetFeature<"bdw", "X86ProcFamily", "IntelBDW", + " Intel Broadwell Processor", [ + ProcIntelHSW, FeatureADX, FeatureRDSEED, - FeatureSlowIncDec, - FeatureLAHFSAHF + FeatureSMAP ]>; +class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, + [ProcIntelBDW]>; def : BroadwellProc<"broadwell">; +def ProcIntelSKL : SubtargetFeature<"skl", "X86ProcFamily", "IntelSKL", + " Intel Skylake Client Processor", [ + ProcIntelBDW, + FeatureMPX, + FeatureXSAVEC, + FeatureXSAVES, + FeatureSGX, + FeatureCLFLUSHOPT +]>; + +// FIXME: define SKL model +class SkylakeClientProc<string Name> : ProcessorModel<Name, HaswellModel, + [ProcIntelSKL]>; +def : SkylakeClientProc<"skl">; + // FIXME: define KNL model -class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [ - FeatureMMX, +class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,[ + ProcIntelIVB, FeatureAVX512, - FeatureFXSR, FeatureERI, FeatureCDI, FeaturePFI, - FeatureCMPXCHG16B, - FeaturePOPCNT, - FeatureAES, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureRDRAND, - FeatureF16C, - FeatureFSGSBase, + FeaturePREFETCHWT1, + FeatureADX, + FeatureRDSEED, FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureBMI2, - FeatureFMA, - FeatureRTM, - FeatureHLE, - FeatureSlowIncDec, - FeatureMPX, - FeatureLAHFSAHF + FeatureFMA ]>; def : KnightsLandingProc<"knl">; -// FIXME: define SKX model -class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [ - FeatureMMX, +def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", "IntelSKX", + " Intel Skylake Server Processor", [ + ProcIntelSKL, FeatureAVX512, - FeatureFXSR, FeatureCDI, FeatureDQI, FeatureBWI, FeatureVLX, FeaturePKU, - FeatureCMPXCHG16B, - FeatureSlowBTMem, - FeaturePOPCNT, - FeatureAES, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureRDRAND, - FeatureF16C, - FeatureFSGSBase, - FeatureMOVBE, - FeatureLZCNT, - FeatureBMI, - FeatureBMI2, - FeatureFMA, - FeatureRTM, - FeatureHLE, - FeatureADX, - FeatureRDSEED, - FeatureSlowIncDec, - FeatureMPX, - FeatureXSAVEC, - FeatureXSAVES, - FeatureLAHFSAHF + FeaturePCOMMIT, + FeatureCLWB ]>; -def : SkylakeProc<"skylake">; -def : SkylakeProc<"skx">; // Legacy alias. -class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel, [ - FeatureMMX, - FeatureAVX512, - FeatureFXSR, - FeatureCDI, - FeatureDQI, - FeatureBWI, - FeatureVLX, - FeaturePKU, - FeatureCMPXCHG16B, - FeatureSlowBTMem, - FeaturePOPCNT, - FeatureAES, - FeaturePCLMUL, - FeatureXSAVE, - FeatureXSAVEOPT, - FeatureRDRAND, - FeatureF16C, - FeatureFSGSBase, - FeatureMOVBE, - FeatureLZCNT, - FeatureBMI, - FeatureBMI2, +// FIXME: define SKX model +class SkylakeServerProc<string Name> : ProcessorModel<Name, HaswellModel, + [ ProcIntelSKX]>; +def : SkylakeServerProc<"skylake">; +def : SkylakeServerProc<"skx">; // Legacy alias. + +def ProcIntelCNL : SubtargetFeature<"cnl", "X86ProcFamily", "IntelCNL", + " Intel Cannonlake Processor", [ + ProcIntelSKX, FeatureVBMI, - FeatureFMA, - FeatureRTM, - FeatureHLE, - FeatureADX, - FeatureRDSEED, - FeatureSlowIncDec, - FeatureMPX, - FeatureXSAVEC, - FeatureXSAVES, - FeatureLAHFSAHF + FeatureIFMA, + FeatureSHA ]>; + +class CannonlakeProc<string Name> : ProcessorModel<Name, HaswellModel, + [ ProcIntelCNL ]>; def : CannonlakeProc<"cannonlake">; def : CannonlakeProc<"cnl">; |
