diff options
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
14 files changed, 169 insertions, 169 deletions
diff --git a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp index 2a357238deb..15532d7ff1a 100644 --- a/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp @@ -40,7 +40,7 @@ WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI, void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { assert(RegNo != WebAssemblyFunctionInfo::UnusedReg); - // Note that there's an implicit get_local/set_local here! + // Note that there's an implicit local.get/local.set here! OS << "$" << RegNo; } @@ -292,8 +292,8 @@ const char *llvm::WebAssembly::anyTypeToString(unsigned Ty) { return "f64"; case wasm::WASM_TYPE_V128: return "v128"; - case wasm::WASM_TYPE_ANYFUNC: - return "anyfunc"; + case wasm::WASM_TYPE_FUNCREF: + return "funcref"; case wasm::WASM_TYPE_FUNC: return "func"; case wasm::WASM_TYPE_EXCEPT_REF: diff --git a/llvm/lib/Target/WebAssembly/README.txt b/llvm/lib/Target/WebAssembly/README.txt index ef0099f07ef..51f341e3581 100644 --- a/llvm/lib/Target/WebAssembly/README.txt +++ b/llvm/lib/Target/WebAssembly/README.txt @@ -120,8 +120,8 @@ code like this: It could be done with a smaller encoding like this: i32.const $push5=, 0 - tee_local $push6=, $4=, $pop5 - copy_local $3=, $pop6 + local.tee $push6=, $4=, $pop5 + local.copy $3=, $pop6 //===---------------------------------------------------------------------===// @@ -180,11 +180,11 @@ floating-point constants. //===---------------------------------------------------------------------===// The function @dynamic_alloca_redzone in test/CodeGen/WebAssembly/userstack.ll -ends up with a tee_local in its prolog which has an unused result, requiring +ends up with a local.tee in its prolog which has an unused result, requiring an extra drop: - get_global $push8=, 0 - tee_local $push9=, 1, $pop8 + global.get $push8=, 0 + local.tee $push9=, 1, $pop8 drop $pop9 [...] diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp index 92cf7f38efa..27aabe6ba0b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp @@ -11,7 +11,7 @@ /// This file converts any remaining registers into WebAssembly locals. /// /// After register stackification and register coloring, convert non-stackified -/// registers into locals, inserting explicit get_local and set_local +/// registers into locals, inserting explicit local.get and local.set /// instructions. /// //===----------------------------------------------------------------------===// @@ -96,54 +96,54 @@ static unsigned getDropOpcode(const TargetRegisterClass *RC) { llvm_unreachable("Unexpected register class"); } -/// Get the appropriate get_local opcode for the given register class. +/// Get the appropriate local.get opcode for the given register class. static unsigned getGetLocalOpcode(const TargetRegisterClass *RC) { if (RC == &WebAssembly::I32RegClass) - return WebAssembly::GET_LOCAL_I32; + return WebAssembly::LOCAL_GET_I32; if (RC == &WebAssembly::I64RegClass) - return WebAssembly::GET_LOCAL_I64; + return WebAssembly::LOCAL_GET_I64; if (RC == &WebAssembly::F32RegClass) - return WebAssembly::GET_LOCAL_F32; + return WebAssembly::LOCAL_GET_F32; if (RC == &WebAssembly::F64RegClass) - return WebAssembly::GET_LOCAL_F64; + return WebAssembly::LOCAL_GET_F64; if (RC == &WebAssembly::V128RegClass) - return WebAssembly::GET_LOCAL_V128; + return WebAssembly::LOCAL_GET_V128; if (RC == &WebAssembly::EXCEPT_REFRegClass) - return WebAssembly::GET_LOCAL_EXCEPT_REF; + return WebAssembly::LOCAL_GET_EXCEPT_REF; llvm_unreachable("Unexpected register class"); } -/// Get the appropriate set_local opcode for the given register class. +/// Get the appropriate local.set opcode for the given register class. static unsigned getSetLocalOpcode(const TargetRegisterClass *RC) { if (RC == &WebAssembly::I32RegClass) - return WebAssembly::SET_LOCAL_I32; + return WebAssembly::LOCAL_SET_I32; if (RC == &WebAssembly::I64RegClass) - return WebAssembly::SET_LOCAL_I64; + return WebAssembly::LOCAL_SET_I64; if (RC == &WebAssembly::F32RegClass) - return WebAssembly::SET_LOCAL_F32; + return WebAssembly::LOCAL_SET_F32; if (RC == &WebAssembly::F64RegClass) - return WebAssembly::SET_LOCAL_F64; + return WebAssembly::LOCAL_SET_F64; if (RC == &WebAssembly::V128RegClass) - return WebAssembly::SET_LOCAL_V128; + return WebAssembly::LOCAL_SET_V128; if (RC == &WebAssembly::EXCEPT_REFRegClass) - return WebAssembly::SET_LOCAL_EXCEPT_REF; + return WebAssembly::LOCAL_SET_EXCEPT_REF; llvm_unreachable("Unexpected register class"); } -/// Get the appropriate tee_local opcode for the given register class. +/// Get the appropriate local.tee opcode for the given register class. static unsigned getTeeLocalOpcode(const TargetRegisterClass *RC) { if (RC == &WebAssembly::I32RegClass) - return WebAssembly::TEE_LOCAL_I32; + return WebAssembly::LOCAL_TEE_I32; if (RC == &WebAssembly::I64RegClass) - return WebAssembly::TEE_LOCAL_I64; + return WebAssembly::LOCAL_TEE_I64; if (RC == &WebAssembly::F32RegClass) - return WebAssembly::TEE_LOCAL_F32; + return WebAssembly::LOCAL_TEE_F32; if (RC == &WebAssembly::F64RegClass) - return WebAssembly::TEE_LOCAL_F64; + return WebAssembly::LOCAL_TEE_F64; if (RC == &WebAssembly::V128RegClass) - return WebAssembly::TEE_LOCAL_V128; + return WebAssembly::LOCAL_TEE_V128; if (RC == &WebAssembly::EXCEPT_REFRegClass) - return WebAssembly::TEE_LOCAL_EXCEPT_REF; + return WebAssembly::LOCAL_TEE_EXCEPT_REF; llvm_unreachable("Unexpected register class"); } @@ -233,8 +233,8 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { if (MI.isDebugInstr() || MI.isLabel()) continue; - // Replace tee instructions with tee_local. The difference is that tee - // instructions have two defs, while tee_local instructions have one def + // Replace tee instructions with local.tee. The difference is that tee + // instructions have two defs, while local.tee instructions have one def // and an index of a local to write to. if (WebAssembly::isTee(MI)) { assert(MFI.isVRegStackified(MI.getOperand(0).getReg())); @@ -253,7 +253,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { MFI.stackifyVReg(NewReg); } - // Replace the TEE with a TEE_LOCAL. + // Replace the TEE with a LOCAL_TEE. unsigned LocalId = getLocalId(Reg2Local, CurLocal, MI.getOperand(1).getReg()); unsigned Opc = getTeeLocalOpcode(RC); @@ -267,7 +267,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { continue; } - // Insert set_locals for any defs that aren't stackified yet. Currently + // Insert local.sets for any defs that aren't stackified yet. Currently // we handle at most one def. assert(MI.getDesc().getNumDefs() <= 1); if (MI.getDesc().getNumDefs() == 1) { @@ -297,7 +297,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { } MI.getOperand(0).setReg(NewReg); // This register operand of the original instruction is now being used - // by the inserted drop or set_local instruction, so make it not dead + // by the inserted drop or local.set instruction, so make it not dead // yet. MI.getOperand(0).setIsDead(false); MFI.stackifyVReg(NewReg); @@ -305,7 +305,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { } } - // Insert get_locals for any uses that aren't stackified yet. + // Insert local.gets for any uses that aren't stackified yet. MachineInstr *InsertPt = &MI; for (MachineOperand &MO : reverse(MI.explicit_uses())) { if (!MO.isReg()) @@ -327,7 +327,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { } // If we see a stackified register, prepare to insert subsequent - // get_locals before the start of its tree. + // local.gets before the start of its tree. if (MFI.isVRegStackified(OldReg)) { InsertPt = findStartOfTree(MO, MRI, MFI); continue; @@ -343,7 +343,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) { continue; } - // Insert a get_local. + // Insert a local.get. unsigned LocalId = getLocalId(Reg2Local, CurLocal, OldReg); const TargetRegisterClass *RC = MRI.getRegClass(OldReg); unsigned NewReg = MRI.createVirtualRegister(RC); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp index 9db34304213..2d5aff28d27 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp @@ -130,7 +130,7 @@ void WebAssemblyFrameLowering::writeSPToGlobal( const char *ES = "__stack_pointer"; auto *SPSymbol = MF.createExternalSymbolName(ES); - BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::SET_GLOBAL_I32)) + BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::GLOBAL_SET_I32)) .addExternalSymbol(SPSymbol, WebAssemblyII::MO_SYMBOL_GLOBAL) .addReg(SrcReg); } @@ -177,7 +177,7 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF, const char *ES = "__stack_pointer"; auto *SPSymbol = MF.createExternalSymbolName(ES); - BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GET_GLOBAL_I32), SPReg) + BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GLOBAL_GET_I32), SPReg) .addExternalSymbol(SPSymbol, WebAssemblyII::MO_SYMBOL_GLOBAL); bool HasBP = hasBP(MF); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 50b2969e252..d267358db30 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -917,7 +917,7 @@ SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op, // the FI to some LEA-like instruction, but since we don't have that, we // need to insert some kind of instruction that can take an FI operand and // produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy - // copy_local between Op and its FI operand. + // local.copy between Op and its FI operand. SDValue Chain = Op.getOperand(0); SDLoc DL(Op); unsigned Reg = cast<RegisterSDNode>(Op.getOperand(1))->getReg(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td index f9d092e4b8a..5fb8ef90bc4 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td @@ -114,7 +114,7 @@ def : LoadPatNoOffset<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>; def : LoadPatNoOffset<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>; def : LoadPatNoOffset<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>; def : LoadPatNoOffset<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>; -// 32->64 sext load gets selected as i32.atomic.load, i64.extend_s/i32 +// 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s // Zero-extending loads with constant offset def : LoadPatImmOff<i32, zext_aload_8_32, regPlusImm, ATOMIC_LOAD8_U_I32>; @@ -344,82 +344,82 @@ multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string Name, int Opcode> { defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0xfe1e>; defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0xfe1f>; defm ATOMIC_RMW8_U_ADD_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8_u.add", 0xfe20>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0xfe20>; defm ATOMIC_RMW16_U_ADD_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16_u.add", 0xfe21>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0xfe21>; defm ATOMIC_RMW8_U_ADD_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8_u.add", 0xfe22>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0xfe22>; defm ATOMIC_RMW16_U_ADD_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16_u.add", 0xfe23>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0xfe23>; defm ATOMIC_RMW32_U_ADD_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32_u.add", 0xfe24>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0xfe24>; defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0xfe25>; defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0xfe26>; defm ATOMIC_RMW8_U_SUB_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8_u.sub", 0xfe27>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0xfe27>; defm ATOMIC_RMW16_U_SUB_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16_u.sub", 0xfe28>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0xfe28>; defm ATOMIC_RMW8_U_SUB_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8_u.sub", 0xfe29>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0xfe29>; defm ATOMIC_RMW16_U_SUB_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16_u.sub", 0xfe2a>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0xfe2a>; defm ATOMIC_RMW32_U_SUB_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32_u.sub", 0xfe2b>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0xfe2b>; defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0xfe2c>; defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0xfe2d>; defm ATOMIC_RMW8_U_AND_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8_u.and", 0xfe2e>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0xfe2e>; defm ATOMIC_RMW16_U_AND_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16_u.and", 0xfe2f>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0xfe2f>; defm ATOMIC_RMW8_U_AND_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8_u.and", 0xfe30>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0xfe30>; defm ATOMIC_RMW16_U_AND_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16_u.and", 0xfe31>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0xfe31>; defm ATOMIC_RMW32_U_AND_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32_u.and", 0xfe32>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0xfe32>; defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0xfe33>; defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0xfe34>; defm ATOMIC_RMW8_U_OR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8_u.or", 0xfe35>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0xfe35>; defm ATOMIC_RMW16_U_OR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16_u.or", 0xfe36>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0xfe36>; defm ATOMIC_RMW8_U_OR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8_u.or", 0xfe37>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0xfe37>; defm ATOMIC_RMW16_U_OR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16_u.or", 0xfe38>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0xfe38>; defm ATOMIC_RMW32_U_OR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32_u.or", 0xfe39>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0xfe39>; defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0xfe3a>; defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0xfe3b>; defm ATOMIC_RMW8_U_XOR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8_u.xor", 0xfe3c>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0xfe3c>; defm ATOMIC_RMW16_U_XOR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16_u.xor", 0xfe3d>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0xfe3d>; defm ATOMIC_RMW8_U_XOR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8_u.xor", 0xfe3e>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0xfe3e>; defm ATOMIC_RMW16_U_XOR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16_u.xor", 0xfe3f>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0xfe3f>; defm ATOMIC_RMW32_U_XOR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32_u.xor", 0xfe40>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0xfe40>; defm ATOMIC_RMW_XCHG_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0xfe41>; defm ATOMIC_RMW_XCHG_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0xfe42>; defm ATOMIC_RMW8_U_XCHG_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8_u.xchg", 0xfe43>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0xfe43>; defm ATOMIC_RMW16_U_XCHG_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16_u.xchg", 0xfe44>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0xfe44>; defm ATOMIC_RMW8_U_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8_u.xchg", 0xfe45>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0xfe45>; defm ATOMIC_RMW16_U_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16_u.xchg", 0xfe46>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0xfe46>; defm ATOMIC_RMW32_U_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32_u.xchg", 0xfe47>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0xfe47>; // Select binary RMWs with no constant offset. class BinRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> : @@ -530,7 +530,7 @@ class sext_bin_rmw_8_64<PatFrag kind> : PatFrag<(ops node:$addr, node:$val), (anyext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>; class sext_bin_rmw_16_64<PatFrag kind> : sext_bin_rmw_8_64<kind>; -// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_s/i32 +// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s // Patterns for various addressing modes for truncating-extending binary RMWs. multiclass BinRMWTruncExtPattern< @@ -677,15 +677,15 @@ defm ATOMIC_RMW_CMPXCHG_I32 : defm ATOMIC_RMW_CMPXCHG_I64 : WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0xfe49>; defm ATOMIC_RMW8_U_CMPXCHG_I32 : - WebAssemblyTerRMW<I32, "i32.atomic.rmw8_u.cmpxchg", 0xfe4a>; + WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0xfe4a>; defm ATOMIC_RMW16_U_CMPXCHG_I32 : - WebAssemblyTerRMW<I32, "i32.atomic.rmw16_u.cmpxchg", 0xfe4b>; + WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0xfe4b>; defm ATOMIC_RMW8_U_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw8_u.cmpxchg", 0xfe4c>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0xfe4c>; defm ATOMIC_RMW16_U_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw16_u.cmpxchg", 0xfe4d>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0xfe4d>; defm ATOMIC_RMW32_U_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw32_u.cmpxchg", 0xfe4e>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0xfe4e>; // Select ternary RMWs with no constant offset. class TerRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> : @@ -790,7 +790,7 @@ class sext_ter_rmw_8_64<PatFrag kind> : (i32 (trunc (i64 node:$exp))), (i32 (trunc (i64 node:$new))))))))>; class sext_ter_rmw_16_64<PatFrag kind> : sext_ter_rmw_8_64<kind>; -// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_s/i32 +// 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s // Patterns for various addressing modes for truncating-extending ternary RMWs. multiclass TerRMWTruncExtPattern< diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td index 0d772c743a7..e128656a142 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrConv.td @@ -15,15 +15,15 @@ defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins), [(set I32:$dst, (trunc I64:$src))], - "i32.wrap/i64\t$dst, $src", "i32.wrap/i64", 0xa7>; + "i32.wrap_i64\t$dst, $src", "i32.wrap_i64", 0xa7>; defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins), [(set I64:$dst, (sext I32:$src))], - "i64.extend_s/i32\t$dst, $src", "i64.extend_s/i32", + "i64.extend_i32_s\t$dst, $src", "i64.extend_i32_s", 0xac>; defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins), [(set I64:$dst, (zext I32:$src))], - "i64.extend_u/i32\t$dst, $src", "i64.extend_u/i32", + "i64.extend_i32_u\t$dst, $src", "i64.extend_i32_u", 0xad>; let Predicates = [HasSignExt] in { @@ -58,43 +58,43 @@ def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>; // overflow or invalid. defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins), [(set I32:$dst, (fp_to_sint F32:$src))], - "i32.trunc_s:sat/f32\t$dst, $src", - "i32.trunc_s:sat/f32", 0xfc00>, + "i32.trunc_sat_f32_s\t$dst, $src", + "i32.trunc_sat_f32_s", 0xfc00>, Requires<[HasNontrappingFPToInt]>; defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins), [(set I32:$dst, (fp_to_uint F32:$src))], - "i32.trunc_u:sat/f32\t$dst, $src", - "i32.trunc_u:sat/f32", 0xfc01>, + "i32.trunc_sat_f32_u\t$dst, $src", + "i32.trunc_sat_f32_u", 0xfc01>, Requires<[HasNontrappingFPToInt]>; defm I64_TRUNC_S_SAT_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins), [(set I64:$dst, (fp_to_sint F32:$src))], - "i64.trunc_s:sat/f32\t$dst, $src", - "i64.trunc_s:sat/f32", 0xfc04>, + "i64.trunc_sat_f32_s\t$dst, $src", + "i64.trunc_sat_f32_s", 0xfc04>, Requires<[HasNontrappingFPToInt]>; defm I64_TRUNC_U_SAT_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins), [(set I64:$dst, (fp_to_uint F32:$src))], - "i64.trunc_u:sat/f32\t$dst, $src", - "i64.trunc_u:sat/f32", 0xfc05>, + "i64.trunc_sat_f32_u\t$dst, $src", + "i64.trunc_sat_f32_u", 0xfc05>, Requires<[HasNontrappingFPToInt]>; defm I32_TRUNC_S_SAT_F64 : I<(outs I32:$dst), (ins F64:$src), (outs), (ins), [(set I32:$dst, (fp_to_sint F64:$src))], - "i32.trunc_s:sat/f64\t$dst, $src", - "i32.trunc_s:sat/f64", 0xfc02>, + "i32.trunc_sat_f64_s\t$dst, $src", + "i32.trunc_sat_f64_s", 0xfc02>, Requires<[HasNontrappingFPToInt]>; defm I32_TRUNC_U_SAT_F64 : I<(outs I32:$dst), (ins F64:$src), (outs), (ins), [(set I32:$dst, (fp_to_uint F64:$src))], - "i32.trunc_u:sat/f64\t$dst, $src", - "i32.trunc_u:sat/f64", 0xfc03>, + "i32.trunc_sat_f64_u\t$dst, $src", + "i32.trunc_sat_f64_u", 0xfc03>, Requires<[HasNontrappingFPToInt]>; defm I64_TRUNC_S_SAT_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins), [(set I64:$dst, (fp_to_sint F64:$src))], - "i64.trunc_s:sat/f64\t$dst, $src", - "i64.trunc_s:sat/f64", 0xfc06>, + "i64.trunc_sat_f64_s\t$dst, $src", + "i64.trunc_sat_f64_s", 0xfc06>, Requires<[HasNontrappingFPToInt]>; defm I64_TRUNC_U_SAT_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins), [(set I64:$dst, (fp_to_uint F64:$src))], - "i64.trunc_u:sat/f64\t$dst, $src", - "i64.trunc_u:sat/f64", 0xfc07>, + "i64.trunc_sat_f64_u\t$dst, $src", + "i64.trunc_sat_f64_u", 0xfc07>, Requires<[HasNontrappingFPToInt]>; // Lower llvm.wasm.trunc.saturate.* to saturating instructions @@ -147,86 +147,86 @@ defm FP_TO_UINT_I64_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins), // Conversion from floating point to integer traps on overflow and invalid. let hasSideEffects = 1 in { defm I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins), - [], "i32.trunc_s/f32\t$dst, $src", "i32.trunc_s/f32", + [], "i32.trunc_f32_s\t$dst, $src", "i32.trunc_f32_s", 0xa8>; defm I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins), - [], "i32.trunc_u/f32\t$dst, $src", "i32.trunc_u/f32", + [], "i32.trunc_f32_u\t$dst, $src", "i32.trunc_f32_u", 0xa9>; defm I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins), - [], "i64.trunc_s/f32\t$dst, $src", "i64.trunc_s/f32", + [], "i64.trunc_f32_s\t$dst, $src", "i64.trunc_f32_s", 0xae>; defm I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src), (outs), (ins), - [], "i64.trunc_u/f32\t$dst, $src", "i64.trunc_u/f32", + [], "i64.trunc_f32_u\t$dst, $src", "i64.trunc_f32_u", 0xaf>; defm I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src), (outs), (ins), - [], "i32.trunc_s/f64\t$dst, $src", "i32.trunc_s/f64", + [], "i32.trunc_f64_s\t$dst, $src", "i32.trunc_f64_s", 0xaa>; defm I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src), (outs), (ins), - [], "i32.trunc_u/f64\t$dst, $src", "i32.trunc_u/f64", + [], "i32.trunc_f64_u\t$dst, $src", "i32.trunc_f64_u", 0xab>; defm I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins), - [], "i64.trunc_s/f64\t$dst, $src", "i64.trunc_s/f64", + [], "i64.trunc_f64_s\t$dst, $src", "i64.trunc_f64_s", 0xb0>; defm I64_TRUNC_U_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins), - [], "i64.trunc_u/f64\t$dst, $src", "i64.trunc_u/f64", + [], "i64.trunc_f64_u\t$dst, $src", "i64.trunc_f64_u", 0xb1>; } // hasSideEffects = 1 defm F32_CONVERT_S_I32 : I<(outs F32:$dst), (ins I32:$src), (outs), (ins), [(set F32:$dst, (sint_to_fp I32:$src))], - "f32.convert_s/i32\t$dst, $src", "f32.convert_s/i32", + "f32.convert_i32_s\t$dst, $src", "f32.convert_i32_s", 0xb2>; defm F32_CONVERT_U_I32 : I<(outs F32:$dst), (ins I32:$src), (outs), (ins), [(set F32:$dst, (uint_to_fp I32:$src))], - "f32.convert_u/i32\t$dst, $src", "f32.convert_u/i32", + "f32.convert_i32_u\t$dst, $src", "f32.convert_i32_u", 0xb3>; defm F64_CONVERT_S_I32 : I<(outs F64:$dst), (ins I32:$src), (outs), (ins), [(set F64:$dst, (sint_to_fp I32:$src))], - "f64.convert_s/i32\t$dst, $src", "f64.convert_s/i32", + "f64.convert_i32_s\t$dst, $src", "f64.convert_i32_s", 0xb7>; defm F64_CONVERT_U_I32 : I<(outs F64:$dst), (ins I32:$src), (outs), (ins), [(set F64:$dst, (uint_to_fp I32:$src))], - "f64.convert_u/i32\t$dst, $src", "f64.convert_u/i32", + "f64.convert_i32_u\t$dst, $src", "f64.convert_i32_u", 0xb8>; defm F32_CONVERT_S_I64 : I<(outs F32:$dst), (ins I64:$src), (outs), (ins), [(set F32:$dst, (sint_to_fp I64:$src))], - "f32.convert_s/i64\t$dst, $src", "f32.convert_s/i64", + "f32.convert_i64_s\t$dst, $src", "f32.convert_i64_s", 0xb4>; defm F32_CONVERT_U_I64 : I<(outs F32:$dst), (ins I64:$src), (outs), (ins), [(set F32:$dst, (uint_to_fp I64:$src))], - "f32.convert_u/i64\t$dst, $src", "f32.convert_u/i64", + "f32.convert_i64_u\t$dst, $src", "f32.convert_i64_u", 0xb5>; defm F64_CONVERT_S_I64 : I<(outs F64:$dst), (ins I64:$src), (outs), (ins), [(set F64:$dst, (sint_to_fp I64:$src))], - "f64.convert_s/i64\t$dst, $src", "f64.convert_s/i64", + "f64.convert_i64_s\t$dst, $src", "f64.convert_i64_s", 0xb9>; defm F64_CONVERT_U_I64 : I<(outs F64:$dst), (ins I64:$src), (outs), (ins), [(set F64:$dst, (uint_to_fp I64:$src))], - "f64.convert_u/i64\t$dst, $src", "f64.convert_u/i64", + "f64.convert_i64_u\t$dst, $src", "f64.convert_i64_u", 0xba>; defm F64_PROMOTE_F32 : I<(outs F64:$dst), (ins F32:$src), (outs), (ins), [(set F64:$dst, (fpextend F32:$src))], - "f64.promote/f32\t$dst, $src", "f64.promote/f32", + "f64.promote_f32\t$dst, $src", "f64.promote_f32", 0xbb>; defm F32_DEMOTE_F64 : I<(outs F32:$dst), (ins F64:$src), (outs), (ins), [(set F32:$dst, (fpround F64:$src))], - "f32.demote/f64\t$dst, $src", "f32.demote/f64", + "f32.demote_f64\t$dst, $src", "f32.demote_f64", 0xb6>; defm I32_REINTERPRET_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins), [(set I32:$dst, (bitconvert F32:$src))], - "i32.reinterpret/f32\t$dst, $src", - "i32.reinterpret/f32", 0xbc>; + "i32.reinterpret_f32\t$dst, $src", + "i32.reinterpret_f32", 0xbc>; defm F32_REINTERPRET_I32 : I<(outs F32:$dst), (ins I32:$src), (outs), (ins), [(set F32:$dst, (bitconvert I32:$src))], - "f32.reinterpret/i32\t$dst, $src", - "f32.reinterpret/i32", 0xbe>; + "f32.reinterpret_i32\t$dst, $src", + "f32.reinterpret_i32", 0xbe>; defm I64_REINTERPRET_F64 : I<(outs I64:$dst), (ins F64:$src), (outs), (ins), [(set I64:$dst, (bitconvert F64:$src))], - "i64.reinterpret/f64\t$dst, $src", - "i64.reinterpret/f64", 0xbd>; + "i64.reinterpret_f64\t$dst, $src", + "i64.reinterpret_f64", 0xbd>; defm F64_REINTERPRET_I64 : I<(outs F64:$dst), (ins I64:$src), (outs), (ins), [(set F64:$dst, (bitconvert I64:$src))], - "f64.reinterpret/i64\t$dst, $src", - "f64.reinterpret/i64", 0xbf>; + "f64.reinterpret_i64\t$dst, $src", + "f64.reinterpret_i64", 0xbf>; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td index 97583ea0e6a..15a9714a55a 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrFormats.td @@ -40,10 +40,10 @@ class NI<dag oops, dag iops, list<dag> pattern, string stack, // based version of this instruction, as well as the corresponding asmstr. // The register versions have virtual-register operands which correspond to wasm // locals or stack locations. Each use and def of the register corresponds to an -// implicit get_local / set_local or access of stack operands in wasm. These +// implicit local.get / local.set or access of stack operands in wasm. These // instructions are used for ISel and all MI passes. The stack versions of the // instructions do not have register operands (they implicitly operate on the -// stack), and get_locals and set_locals are explicit. The register instructions +// stack), and local.gets and local.sets are explicit. The register instructions // are converted to their corresponding stack instructions before lowering to // MC. // Every instruction should want to be based on this multi-class to guarantee diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td index 953dd05fda5..d172537bb34 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -197,49 +197,49 @@ defm "": ARGUMENT<F32, f32>; defm "": ARGUMENT<F64, f64>; defm "": ARGUMENT<EXCEPT_REF, ExceptRef>; -// get_local and set_local are not generated by instruction selection; they +// local.get and local.set are not generated by instruction selection; they // are implied by virtual register uses and defs. multiclass LOCAL<WebAssemblyRegClass vt> { let hasSideEffects = 0 in { - // COPY is not an actual instruction in wasm, but since we allow get_local and - // set_local to be implicit during most of codegen, we can have a COPY which - // is actually a no-op because all the work is done in the implied get_local - // and set_local. COPYs are eliminated (and replaced with - // get_local/set_local) in the ExplicitLocals pass. + // COPY is not an actual instruction in wasm, but since we allow local.get and + // local.set to be implicit during most of codegen, we can have a COPY which + // is actually a no-op because all the work is done in the implied local.get + // and local.set. COPYs are eliminated (and replaced with + // local.get/local.set) in the ExplicitLocals pass. let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [], - "copy_local\t$res, $src", "copy_local">; + "local.copy\t$res, $src", "local.copy">; // TEE is similar to COPY, but writes two copies of its result. Typically // this would be used to stackify one result and write the other result to a // local. let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [], - "tee_local\t$res, $also, $src", "tee_local">; + "local.tee\t$res, $also, $src", "local.tee">; - // This is the actual get_local instruction in wasm. These are made explicit + // This is the actual local.get instruction in wasm. These are made explicit // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm // local, which is a side effect not otherwise modeled in LLVM. let mayLoad = 1, isAsCheapAsAMove = 1 in - defm GET_LOCAL_#vt : I<(outs vt:$res), (ins local_op:$local), + defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local), (outs), (ins local_op:$local), [], - "get_local\t$res, $local", "get_local\t$local", 0x20>; + "local.get\t$res, $local", "local.get\t$local", 0x20>; - // This is the actual set_local instruction in wasm. These are made explicit + // This is the actual local.set instruction in wasm. These are made explicit // by the ExplicitLocals pass. It has mayStore because it writes to a wasm // local, which is a side effect not otherwise modeled in LLVM. let mayStore = 1, isAsCheapAsAMove = 1 in - defm SET_LOCAL_#vt : I<(outs), (ins local_op:$local, vt:$src), + defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src), (outs), (ins local_op:$local), [], - "set_local\t$local, $src", "set_local\t$local", 0x21>; + "local.set\t$local, $src", "local.set\t$local", 0x21>; - // This is the actual tee_local instruction in wasm. TEEs are turned into - // TEE_LOCALs by the ExplicitLocals pass. It has mayStore for the same reason - // as SET_LOCAL. + // This is the actual local.tee instruction in wasm. TEEs are turned into + // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason + // as LOCAL_SET. let mayStore = 1, isAsCheapAsAMove = 1 in - defm TEE_LOCAL_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), + defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), (outs), (ins local_op:$local), [], - "tee_local\t$res, $local, $src", "tee_local\t$local", + "local.tee\t$res, $local, $src", "local.tee\t$local", 0x22>; // Unused values must be dropped in some contexts. @@ -247,15 +247,15 @@ let hasSideEffects = 0 in { "drop\t$src", "drop", 0x1a>; let mayLoad = 1 in - defm GET_GLOBAL_#vt : I<(outs vt:$res), (ins global_op:$local), + defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local), (outs), (ins global_op:$local), [], - "get_global\t$res, $local", "get_global\t$local", + "global.get\t$res, $local", "global.get\t$local", 0x23>; let mayStore = 1 in - defm SET_GLOBAL_#vt : I<(outs), (ins global_op:$local, vt:$src), + defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src), (outs), (ins global_op:$local), [], - "set_global\t$local, $src", "set_global\t$local", + "global.set\t$local, $src", "global.set\t$local", 0x24>; } // hasSideEffects = 0 diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 08d6a5a6c83..b72ac6fa1b1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -773,17 +773,17 @@ multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op, name#"\t$dst, $vec", name, simdop>; } -// Integer to floating point: convert_s / convert_u -defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_s/i32x4", 175>; -defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_u/i32x4", 176>; -defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_s/i64x2", 177>; -defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_u/i64x2", 178>; - -// Floating point to integer with saturation: trunc_sat_s / trunc_sat_u -defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_s/f32x4", 171>; -defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_u/f32x4", 172>; -defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_s/f64x2", 173>; -defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_u/f64x2", 174>; +// Integer to floating point: convert +defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>; +defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>; +defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>; +defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>; + +// Floating point to integer with saturation: trunc_sat +defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>; +defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>; +defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>; +defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>; // Lower llvm.wasm.trunc.saturate.* to saturating instructions def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))), diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp index 871e92082a4..258d45997fe 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp @@ -287,7 +287,7 @@ bool WebAssemblyLateEHPrepare::addRethrows(MachineFunction &MF) { // %exn = catch 0 // call @__clang_call_terminate(%exn) // unreachable -// (There can be set_local and get_locals before the call if we didn't run +// (There can be local.set and local.gets before the call if we didn't run // RegStackify) // But code transformations can change or add more control flow, so the call to // __clang_call_terminate() function may not be in the original EH pad anymore. @@ -326,7 +326,7 @@ bool WebAssemblyLateEHPrepare::ensureSingleBBTermPads(MachineFunction &MF) { // This runs after hoistCatches(), so catch instruction should be at the top assert(WebAssembly::isCatch(*Catch)); // Takes the result register of the catch instruction as argument. There may - // have been some other set_local/get_locals in between, but at this point + // have been some other local.set/local.gets in between, but at this point // we don't care. Call->getOperand(1).setReg(Catch->getOperand(0).getReg()); auto InsertPos = std::next(MachineBasicBlock::iterator(Catch)); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index ba69d6c5322..ceb024b4be0 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -425,8 +425,8 @@ static bool OneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse, // Actually, dominating is over-conservative. Test that the use would // happen after the one selected use in the stack evaluation order. // - // This is needed as a consequence of using implicit get_locals for - // uses and implicit set_locals for defs. + // This is needed as a consequence of using implicit local.gets for + // uses and implicit local.sets for defs. if (UseInst->getDesc().getNumDefs() == 0) return false; const MachineOperand &MO = UseInst->getOperand(0); @@ -628,7 +628,7 @@ static MachineInstr *RematerializeCheapDef( /// INST ..., Reg, ... /// INST ..., Reg, ... /// -/// with DefReg and TeeReg stackified. This eliminates a get_local from the +/// with DefReg and TeeReg stackified. This eliminates a local.get from the /// resulting code. static MachineInstr *MoveAndTeeForMultiUse( unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, @@ -739,8 +739,8 @@ public: /// operand in the tree that we haven't visited yet. Moving a definition of /// Reg to a point in the tree after that would change its value. /// - /// This is needed as a consequence of using implicit get_locals for - /// uses and implicit set_locals for defs. + /// This is needed as a consequence of using implicit local.gets for + /// uses and implicit local.sets for defs. bool IsOnStack(unsigned Reg) const { for (const RangeTy &Range : Worklist) for (const MachineOperand &MO : Range) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp index de104d42be4..fba1735acad 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp @@ -15,7 +15,7 @@ /// the store's result value, making the stored value register more likely to /// be single-use, thus more likely to be useful to register stackifying, and /// potentially also exposing the store to register stackifying. These both can -/// reduce get_local/set_local traffic. +/// reduce local.get/local.set traffic. /// /// This pass also performs this optimization for memcpy, memmove, and memset /// calls, since the LLVM intrinsics for these return void so they can't use the diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 05bd5926ef9..db8cd81f78a 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -326,7 +326,7 @@ void WebAssemblyPassConfig::addPreEmitPass() { addPass(createWebAssemblyRegColoring()); } - // Insert explicit get_local and set_local operators. + // Insert explicit local.get and local.set operators. addPass(createWebAssemblyExplicitLocals()); // Sort the blocks of the CFG into topological order, a prerequisite for |
