diff options
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td | 102 |
1 files changed, 51 insertions, 51 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td index 1a67b0aef4a..cdc72b69122 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td @@ -23,66 +23,66 @@ // types when loading, and truncate when storing. // Basic load. -def LOAD_I32_ : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (load I32:$addr))]>; -def LOAD_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (load I32:$addr))]>; -def LOAD_F32_ : I<(outs F32:$dst), (ins I32:$addr), - [(set F32:$dst, (load I32:$addr))]>; -def LOAD_F64_ : I<(outs F64:$dst), (ins I32:$addr), - [(set F64:$dst, (load I32:$addr))]>; +def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr), + [(set I32:$dst, (load I32:$addr))]>; +def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (load I32:$addr))]>; +def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr), + [(set F32:$dst, (load I32:$addr))]>; +def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr), + [(set F64:$dst, (load I32:$addr))]>; // Extending load. -def LOAD_S_i8_I32_ : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (sextloadi8 I32:$addr))]>; -def LOAD_U_i8_I32_ : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (zextloadi8 I32:$addr))]>; -def LOAD_S_i16_I32_ : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (sextloadi16 I32:$addr))]>; -def LOAD_U_i16_I32_ : I<(outs I32:$dst), (ins I32:$addr), - [(set I32:$dst, (zextloadi16 I32:$addr))]>; -def LOAD_S_i8_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (sextloadi8 I32:$addr))]>; -def LOAD_U_i8_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (zextloadi8 I32:$addr))]>; -def LOAD_S_i16_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (sextloadi16 I32:$addr))]>; -def LOAD_U_i16_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (zextloadi16 I32:$addr))]>; -def LOAD_S_I32_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (sextloadi32 I32:$addr))]>; -def LOAD_U_I32_I64_ : I<(outs I64:$dst), (ins I32:$addr), - [(set I64:$dst, (zextloadi32 I32:$addr))]>; +def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$addr), + [(set I32:$dst, (sextloadi8 I32:$addr))]>; +def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$addr), + [(set I32:$dst, (zextloadi8 I32:$addr))]>; +def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr), + [(set I32:$dst, (sextloadi16 I32:$addr))]>; +def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr), + [(set I32:$dst, (zextloadi16 I32:$addr))]>; +def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (sextloadi8 I32:$addr))]>; +def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (zextloadi8 I32:$addr))]>; +def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (sextloadi16 I32:$addr))]>; +def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (zextloadi16 I32:$addr))]>; +def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (sextloadi32 I32:$addr))]>; +def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr), + [(set I64:$dst, (zextloadi32 I32:$addr))]>; // "Don't care" extending load become zero-extending load. -def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD_U_i8_I32_ $addr)>; -def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD_U_i16_I32_ $addr)>; -def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD_U_i8_I64_ $addr)>; -def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD_U_i16_I64_ $addr)>; -def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD_U_I32_I64_ $addr)>; +def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 $addr)>; +def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>; +def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 $addr)>; +def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>; +def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>; // Basic store. // Note: WebAssembly inverts SelectionDAG's usual operand order. -def STORE_I32_ : I<(outs), (ins I32:$addr, I32:$val), - [(store i32:$val, I32:$addr)]>; -def STORE_I64_ : I<(outs), (ins I32:$addr, I64:$val), - [(store i64:$val, I32:$addr)]>; -def STORE_F32_ : I<(outs), (ins I32:$addr, F32:$val), - [(store f32:$val, I32:$addr)]>; -def STORE_F64_ : I<(outs), (ins I32:$addr, F64:$val), - [(store f64:$val, I32:$addr)]>; +def STORE_I32 : I<(outs), (ins I32:$addr, I32:$val), + [(store i32:$val, I32:$addr)]>; +def STORE_I64 : I<(outs), (ins I32:$addr, I64:$val), + [(store i64:$val, I32:$addr)]>; +def STORE_F32 : I<(outs), (ins I32:$addr, F32:$val), + [(store f32:$val, I32:$addr)]>; +def STORE_F64 : I<(outs), (ins I32:$addr, F64:$val), + [(store f64:$val, I32:$addr)]>; // Truncating store. -def STORE_i8_I32 : I<(outs), (ins I32:$addr, I32:$val), - [(truncstorei8 I32:$val, I32:$addr)]>; -def STORE_i16_I32 : I<(outs), (ins I32:$addr, I32:$val), - [(truncstorei16 I32:$val, I32:$addr)]>; -def STORE_i8_I64 : I<(outs), (ins I32:$addr, I64:$val), - [(truncstorei8 I64:$val, I32:$addr)]>; -def STORE_i16_I64 : I<(outs), (ins I32:$addr, I64:$val), - [(truncstorei16 I64:$val, I32:$addr)]>; -def STORE_I32_I64 : I<(outs), (ins I32:$addr, I64:$val), - [(truncstorei32 I64:$val, I32:$addr)]>; +def STORE8_I32 : I<(outs), (ins I32:$addr, I32:$val), + [(truncstorei8 I32:$val, I32:$addr)]>; +def STORE16_I32 : I<(outs), (ins I32:$addr, I32:$val), + [(truncstorei16 I32:$val, I32:$addr)]>; +def STORE8_I64 : I<(outs), (ins I32:$addr, I64:$val), + [(truncstorei8 I64:$val, I32:$addr)]>; +def STORE16_I64 : I<(outs), (ins I32:$addr, I64:$val), + [(truncstorei16 I64:$val, I32:$addr)]>; +def STORE32_I64 : I<(outs), (ins I32:$addr, I64:$val), + [(truncstorei32 I64:$val, I32:$addr)]>; // Page size. def page_size_I32 : I<(outs I32:$dst), (ins), |
