diff options
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index 991a5a5773a..bf5582a11f0 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -20,8 +20,12 @@ def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; // Custom nodes for custom operations def wasm_shuffle_t : SDTypeProfile<1, 18, []>; +def wasm_bitselect_t : SDTypeProfile<1, 3, + [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>] +>; def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>; def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; +def wasm_bitselect : SDNode<"WebAssemblyISD::BITSELECT", wasm_bitselect_t>; def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>; def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>; @@ -193,6 +197,16 @@ multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> { )], "v128.not\t$dst, $vec", "v128.not", 63>; } +multiclass Bitselect<ValueType vec_t> { + defm BITSELECT_#vec_t : + SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), + [(set (vec_t V128:$dst), + (vec_t (wasm_bitselect + (vec_t V128:$c), (vec_t V128:$v1), (vec_t V128:$v2) + )) + )], + "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 64>; +} multiclass SIMDReduceVec<ValueType vec_t, string vec, string name, SDNode op, bits<32> simdop> { defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), @@ -380,6 +394,9 @@ defm "" : SIMDNot<v8i16, splat8, i32>; defm "" : SIMDNot<v4i32, splat4, i32>; defm "" : SIMDNot<v2i64, splat2, i64>; +foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in +defm "" : Bitselect<vec_t>; + defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>; defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>; @@ -443,6 +460,13 @@ def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>; } +// Bitselect is equivalent to (c & v1) | (~c & v2) +foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in + def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)), + (and (vnot V128:$c), (vec_t V128:$v2)))), + (!cast<Instruction>("BITSELECT_"#vec_t) + V128:$v1, V128:$v2, V128:$c)>; + // Lower float comparisons that don't care about NaN to standard // WebAssembly float comparisons. These instructions are generated in // the target-independent expansion of unordered comparisons and |
