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-rw-r--r--llvm/lib/Target/Target.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td
index 46a1b470c49..d4b83f40202 100644
--- a/llvm/lib/Target/Target.td
+++ b/llvm/lib/Target/Target.td
@@ -163,6 +163,7 @@ class Instruction {
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+ bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
InstrItinClass Itinerary; // Execution steps used for scheduling.
}
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