diff options
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index d97a92dd109..57a620bca78 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1584,7 +1584,7 @@ let Uses = [CC] in def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; // Set CC and program mask from a register. -let Defs = [CC] in +let hasSideEffects = 1, Defs = [CC] in def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; // Branch and link - like BAS, but also extracts CC and program mask. @@ -1598,9 +1598,11 @@ let Defs = [CC] in def TAM : SideEffectInherentE<"tam", 0x010B>; // Set addressing mode. -def SAM24 : SideEffectInherentE<"sam24", 0x010C>; -def SAM31 : SideEffectInherentE<"sam31", 0x010D>; -def SAM64 : SideEffectInherentE<"sam64", 0x010E>; +let hasSideEffects = 1 in { + def SAM24 : SideEffectInherentE<"sam24", 0x010C>; + def SAM31 : SideEffectInherentE<"sam31", 0x010D>; + def SAM64 : SideEffectInherentE<"sam64", 0x010E>; +} // Branch and set mode. Not really a call, but also sets an output register. let isBranch = 1, isTerminator = 1, isBarrier = 1 in @@ -1614,7 +1616,7 @@ let isCall = 1, Defs = [CC] in // Transactional execution //===----------------------------------------------------------------------===// -let Predicates = [FeatureTransactionalExecution] in { +let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { // Transaction Begin let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; @@ -1633,12 +1635,10 @@ let Predicates = [FeatureTransactionalExecution] in { def TABORT : SideEffectUnaryS<"tabort", 0xB2FC, int_s390_tabort>; // Nontransactional Store - let hasSideEffects = 1 in - def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; + def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; // Extract Transaction Nesting Depth - let hasSideEffects = 1 in - def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; + def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; } //===----------------------------------------------------------------------===// @@ -1646,7 +1646,8 @@ let Predicates = [FeatureTransactionalExecution] in { //===----------------------------------------------------------------------===// let Predicates = [FeatureProcessorAssist] in { - def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; + let hasSideEffects = 1 in + def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; def : Pat<(int_s390_ppa_txassist GR32:$src), (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 0, 1)>; @@ -1685,7 +1686,7 @@ let mayLoad = 1, Defs = [CC] in defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; // Supervisor call. -let isCall = 1, Defs = [CC] in +let hasSideEffects = 1, isCall = 1, Defs = [CC] in def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>; // Store clock. @@ -1700,15 +1701,17 @@ let hasSideEffects = 1, Defs = [CC] in def STFLE : StoreInherentS<"stfle", 0xB2B0>; // Extract CPU time. -let Defs = [R0D, R1D], mayLoad = 1 in +let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>; // Execute. -def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; -def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; +let hasSideEffects = 1 in { + def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; + def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; +} // Program return. -let Defs = [CC] in +let hasSideEffects = 1, Defs = [CC] in def PR : SideEffectInherentE<"pr", 0x0101>; // Move with key. |
