summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp')
-rw-r--r--llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp b/llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
index 344dc17aafd..2e3530c3cf2 100644
--- a/llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
+++ b/llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
@@ -1480,11 +1480,11 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
- BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
+ BuildMI (BB, V8::WRYrr, 2).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
- BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
+ BuildMI (BB, V8::WRYrr, 2).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}
OpenPOWER on IntegriCloud