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-rw-r--r--llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp14
-rw-r--r--llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp24
-rw-r--r--llvm/lib/Target/Sparc/SparcAsmPrinter.cpp14
-rw-r--r--llvm/lib/Target/Sparc/SparcMCInstLower.cpp6
4 files changed, 29 insertions, 29 deletions
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 7e979e50e97..92311026c8c 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -250,7 +250,7 @@ public:
void addRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
+ Inst.addOperand(MCOperand::createReg(getReg()));
}
void addImmOperands(MCInst &Inst, unsigned N) const {
@@ -262,26 +262,26 @@ public:
void addExpr(MCInst &Inst, const MCExpr *Expr) const{
// Add as immediate when possible. Null MCExpr = 0.
if (!Expr)
- Inst.addOperand(MCOperand::CreateImm(0));
+ Inst.addOperand(MCOperand::createImm(0));
else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
+ Inst.addOperand(MCOperand::createImm(CE->getValue()));
else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
+ Inst.addOperand(MCOperand::createExpr(Expr));
}
void addMEMrrOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBase()));
+ Inst.addOperand(MCOperand::createReg(getMemBase()));
assert(getMemOffsetReg() != 0 && "Invalid offset");
- Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
+ Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
}
void addMEMriOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getMemBase()));
+ Inst.addOperand(MCOperand::createReg(getMemBase()));
const MCExpr *Expr = getMemOff();
addExpr(Inst, Expr);
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index 8a6f3a65001..3dedfd7bde0 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -113,7 +113,7 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = IntRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -124,7 +124,7 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = IntRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -136,7 +136,7 @@ static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = FPRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -148,7 +148,7 @@ static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = DFPRegDecoderTable[RegNo];
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -163,7 +163,7 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
unsigned Reg = QFPRegDecoderTable[RegNo];
if (Reg == ~0U)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -172,7 +172,7 @@ static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
const void *Decoder) {
if (RegNo > 3)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo]));
+ Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
return MCDisassembler::Success;
}
@@ -280,7 +280,7 @@ static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
// Decode imm|rs2.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
@@ -358,14 +358,14 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
tgt <<= 2;
if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
0, 30, MI, Decoder))
- MI.addOperand(MCOperand::CreateImm(tgt));
+ MI.addOperand(MCOperand::createImm(tgt));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
uint64_t Address, const void *Decoder) {
unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
- MI.addOperand(MCOperand::CreateImm(tgt));
+ MI.addOperand(MCOperand::createImm(tgt));
return MCDisassembler::Success;
}
@@ -394,7 +394,7 @@ static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
// Decode RS1 | SIMM13.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
@@ -422,7 +422,7 @@ static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
// Decode RS2 | SIMM13.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
@@ -456,7 +456,7 @@ static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
// Decode RS1 | SIMM13.
if (isImm)
- MI.addOperand(MCOperand::CreateImm(simm13));
+ MI.addOperand(MCOperand::createImm(simm13));
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
index 5bfa2878896..e90988d2169 100644
--- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -81,7 +81,7 @@ static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Sym,
OutContext);
const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, OutContext);
- return MCOperand::CreateExpr(expr);
+ return MCOperand::createExpr(expr);
}
static MCOperand createPCXCallOP(MCSymbol *Label,
@@ -104,7 +104,7 @@ static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext);
const SparcMCExpr *expr = SparcMCExpr::Create(Kind,
Add, OutContext);
- return MCOperand::CreateExpr(expr);
+ return MCOperand::createExpr(expr);
}
static void EmitCall(MCStreamer &OutStreamer,
@@ -182,7 +182,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
assert(MO.getReg() != SP::O7 &&
"%o7 is assigned as destination for getpcx!");
- MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
+ MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
if (TM.getRelocationModel() != Reloc::PIC_) {
@@ -199,7 +199,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
EmitHiLo(*OutStreamer, GOTLabel,
SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
MCRegOP, OutContext, STI);
- MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(12,
+ MCOperand imm = MCOperand::createExpr(MCConstantExpr::Create(12,
OutContext));
EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
@@ -211,11 +211,11 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
EmitHiLo(*OutStreamer, GOTLabel,
SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
MCRegOP, OutContext, STI);
- MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(32,
+ MCOperand imm = MCOperand::createExpr(MCConstantExpr::Create(32,
OutContext));
EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
// Use register %o7 to load the lower 32 bits.
- MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
+ MCOperand RegO7 = MCOperand::createReg(SP::O7);
EmitHiLo(*OutStreamer, GOTLabel,
SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
RegO7, OutContext, STI);
@@ -229,7 +229,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
MCSymbol *EndLabel = OutContext.CreateTempSymbol();
MCSymbol *SethiLabel = OutContext.CreateTempSymbol();
- MCOperand RegO7 = MCOperand::CreateReg(SP::O7);
+ MCOperand RegO7 = MCOperand::createReg(SP::O7);
// <StartLabel>:
// call <EndLabel>
diff --git a/llvm/lib/Target/Sparc/SparcMCInstLower.cpp b/llvm/lib/Target/Sparc/SparcMCInstLower.cpp
index 9e94d2c3140..9388d594973 100644
--- a/llvm/lib/Target/Sparc/SparcMCInstLower.cpp
+++ b/llvm/lib/Target/Sparc/SparcMCInstLower.cpp
@@ -63,7 +63,7 @@ static MCOperand LowerSymbolOperand(const MachineInstr *MI,
AP.OutContext);
const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym,
AP.OutContext);
- return MCOperand::CreateExpr(expr);
+ return MCOperand::createExpr(expr);
}
static MCOperand LowerOperand(const MachineInstr *MI,
@@ -74,10 +74,10 @@ static MCOperand LowerOperand(const MachineInstr *MI,
case MachineOperand::MO_Register:
if (MO.isImplicit())
break;
- return MCOperand::CreateReg(MO.getReg());
+ return MCOperand::createReg(MO.getReg());
case MachineOperand::MO_Immediate:
- return MCOperand::CreateImm(MO.getImm());
+ return MCOperand::createImm(MO.getImm());
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
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