diff options
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 22 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstr64Bit.td | 30 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrAliases.td | 119 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.td | 11 |
5 files changed, 178 insertions, 15 deletions
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 8ae10c801cd..cc6c983f585 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -537,9 +537,29 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op) Parser.Lex(); // Eat the '%'. unsigned RegNo; if (matchRegisterName(Parser.getTok(), RegNo, false, false)) { + StringRef name = Parser.getTok().getString(); Parser.Lex(); // Eat the identifier token. E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E); + switch (RegNo) { + default: + Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E); + break; + case Sparc::Y: + Op = SparcOperand::CreateToken("%y", S); + break; + + case Sparc::ICC: + if (name == "xcc") + Op = SparcOperand::CreateToken("%xcc", S); + else + Op = SparcOperand::CreateToken("%icc", S); + break; + + case Sparc::FCC: + assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet"); + Op = SparcOperand::CreateToken("%fcc0", S); + break; + } break; } if (matchSparcAsmModifiers(EVal, E)) { diff --git a/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp index 77404f83146..5e39bd6cb1f 100644 --- a/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ b/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -82,6 +82,17 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { int CC = (int)MI->getOperand(opNum).getImm(); + switch (MI->getOpcode()) { + default: break; + case SP::FBCOND: + case SP::MOVFCCrr: + case SP::MOVFCCri: + case SP::FMOVS_FCC: + case SP::FMOVD_FCC: + case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag. + CC = (CC < 16) ? (CC + 16) : CC; + break; + } O << SPARCCondCodeToString((SPCC::CondCodes)CC); } diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 7ccbd9ea1dc..3ff881d7e04 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -333,32 +333,42 @@ class XBranchSP<dag ins, string asmstr, list<dag> pattern> let Predicates = [Is64Bit] in { let Uses = [ICC] in -def BPXCC : XBranchSP<(ins brtarget:$imm22, CCOp:$cond), - "b$cond %xcc, $imm22", - [(SPbrxcc bb:$imm22, imm:$cond)]>; +def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond), + "b$cond %xcc, $imm19", + [(SPbrxcc bb:$imm19, imm:$cond)]>; // Conditional moves on %xcc. let Uses = [ICC], Constraints = "$f = $rd" in { -def MOVXCCrr : Pseudo<(outs IntRegs:$rd), +let cc = 0b110 in { +def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), "mov$cond %xcc, $rs2, $rd", [(set i32:$rd, (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; -def MOVXCCri : Pseudo<(outs IntRegs:$rd), - (ins i32imm:$i, IntRegs:$f, CCOp:$cond), - "mov$cond %xcc, $i, $rd", +def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), + (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), + "mov$cond %xcc, $simm11, $rd", [(set i32:$rd, - (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>; -def FMOVS_XCC : Pseudo<(outs FPRegs:$rd), + (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; +} // cc + +let opf_cc = 0b110 in { +def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), "fmovs$cond %xcc, $rs2, $rd", [(set f32:$rd, (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; -def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd), +def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), "fmovd$cond %xcc, $rs2, $rd", [(set f64:$rd, (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; +def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), + (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), + "fmovq$cond %xcc, $rs2, $rd", + [(set f128:$rd, + (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; +} // opf_cc } // Uses, Constraints //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td new file mode 100644 index 00000000000..3a489f40ada --- /dev/null +++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -0,0 +1,119 @@ +//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains instruction aliases for Sparc. +//===----------------------------------------------------------------------===// + +// Instruction aliases for conditional moves. + +// mov<cond> <ccreg> rs2, rd +multiclass cond_mov_alias<string cond, int condVal, string ccreg, + Instruction movrr, Instruction movri, + Instruction fmovs, Instruction fmovd> { + + // mov<cond> (%icc|%xcc|%fcc0), rs2, rd + def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), + ", $rs2, $rd"), + (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; + + // mov<cond> (%icc|%xcc|%fcc0), simm11, rd + def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), + ", $simm11, $rd"), + (movri IntRegs:$rd, i32imm:$simm11, condVal)>; + + // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd + def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg), + ", $rs2, $rd"), + (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; + + // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd + def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg), + ", $rs2, $rd"), + (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>; +} + + +// Instruction aliases for integer conditional branches and moves. +multiclass int_cond_alias<string cond, int condVal> { + + // b<cond> $imm + def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"), + (BCOND brtarget:$imm, condVal)>; + + // b<cond> %xcc, $imm + def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"), + (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>; + + defm : cond_mov_alias<cond, condVal, " %icc", + MOVICCrr, MOVICCri, + FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>; + + defm : cond_mov_alias<cond, condVal, " %xcc", + MOVXCCrr, MOVXCCri, + FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>; + + // fmovq<cond> (%icc|%xcc), $rs2, $rd + def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"), + (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, + Requires<[HasV9, HasHardQuad]>; + def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"), + (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, + Requires<[Is64Bit, HasHardQuad]>; + +} + + +// Instruction aliases for floating point conditional branches and moves. +multiclass fp_cond_alias<string cond, int condVal> { + + // fb<cond> $imm + def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"), + (FBCOND brtarget:$imm, condVal), 0>; + + defm : cond_mov_alias<cond, condVal, " %fcc0", + MOVFCCrr, MOVFCCri, + FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>; + + // fmovq<cond> %fcc0, $rs2, $rd + def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"), + (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, + Requires<[HasV9, HasHardQuad]>; +} + +defm : int_cond_alias<"a", 0b1000>; +defm : int_cond_alias<"n", 0b0000>; +defm : int_cond_alias<"ne", 0b1001>; +defm : int_cond_alias<"e", 0b0001>; +defm : int_cond_alias<"g", 0b1010>; +defm : int_cond_alias<"le", 0b0010>; +defm : int_cond_alias<"ge", 0b1011>; +defm : int_cond_alias<"l", 0b0011>; +defm : int_cond_alias<"gu", 0b1100>; +defm : int_cond_alias<"leu", 0b0100>; +defm : int_cond_alias<"cc", 0b1101>; +defm : int_cond_alias<"cs", 0b0101>; +defm : int_cond_alias<"pos", 0b1110>; +defm : int_cond_alias<"neg", 0b0110>; +defm : int_cond_alias<"vc", 0b1111>; +defm : int_cond_alias<"vs", 0b0111>; + +defm : fp_cond_alias<"u", 0b0111>; +defm : fp_cond_alias<"g", 0b0110>; +defm : fp_cond_alias<"ug", 0b0101>; +defm : fp_cond_alias<"l", 0b0100>; +defm : fp_cond_alias<"ul", 0b0011>; +defm : fp_cond_alias<"lg", 0b0010>; +defm : fp_cond_alias<"ne", 0b0001>; +defm : fp_cond_alias<"e", 0b1001>; +defm : fp_cond_alias<"ue", 0b1010>; +defm : fp_cond_alias<"ge", 0b1011>; +defm : fp_cond_alias<"uge", 0b1100>; +defm : fp_cond_alias<"le", 0b1101>; +defm : fp_cond_alias<"ule", 0b1110>; +defm : fp_cond_alias<"o", 0b1111>; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 7808a1aea4c..a884adfee87 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -928,8 +928,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in { def FMOVQ_ICC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), - "fmovd$cond %icc, $rs2, $rd", - [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>; + "fmovq$cond %icc, $rs2, $rd", + [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>, + Requires<[HasHardQuad]>; } let Uses = [FCC], opf_cc = 0b000 in { @@ -946,8 +947,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd" in { def FMOVQ_FCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), - "fmovd$cond %fcc0, $rs2, $rd", - [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>; + "fmovq$cond %fcc0, $rs2, $rd", + [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>, + Requires<[HasHardQuad]>; } } @@ -1092,3 +1094,4 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; include "SparcInstr64Bit.td" +include "SparcInstrAliases.td" |
