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-rw-r--r--llvm/lib/Target/Sparc/Sparc.cpp10
-rw-r--r--llvm/lib/Target/Sparc/SparcInternals.h17
-rw-r--r--llvm/lib/Target/Sparc/SparcV9RegInfo.h2
3 files changed, 8 insertions, 21 deletions
diff --git a/llvm/lib/Target/Sparc/Sparc.cpp b/llvm/lib/Target/Sparc/Sparc.cpp
index cf09734e81b..f1be4060be1 100644
--- a/llvm/lib/Target/Sparc/Sparc.cpp
+++ b/llvm/lib/Target/Sparc/Sparc.cpp
@@ -8,12 +8,16 @@
// 7/15/01 - Vikram Adve - Created
//**************************************************************************/
-#include "llvm/CodeGen/Sparc.h"
+#include "llvm/Target/Sparc.h"
#include "SparcInternals.h"
#include "llvm/Method.h"
#include "llvm/CodeGen/InstrScheduling.h"
#include "llvm/CodeGen/InstrSelection.h"
+// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
+// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
+//
+TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
//---------------------------------------------------------------------------
@@ -115,7 +119,3 @@ bool UltraSparc::compileMethod(Method *M) {
return false;
}
-// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
-// that implements the Sparc backend.
-//
-TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h
index f9a344b37af..e4f0a8bd10a 100644
--- a/llvm/lib/Target/Sparc/SparcInternals.h
+++ b/llvm/lib/Target/Sparc/SparcInternals.h
@@ -8,11 +8,10 @@
#ifndef SPARC_INTERNALS_H
#define SPARC_INTERNALS_H
-#include "llvm/Target/Machine.h"
#include "SparcRegInfo.h"
-
-#include <sys/types.h>
+#include "llvm/Target/SchedInfo.h"
#include "llvm/Type.h"
+#include <sys/types.h>
class UltraSparc;
@@ -39,17 +38,6 @@ enum SparcInstrSchedClass {
SPARC_NUM_SCHED_CLASSES = SPARC_INV
};
-// inline operator int (const SparcInstrSchedClass& si) {
-// return (int) si;
-// }
-//
-// inline operator SparcInstrSchedClass (int i) {
-// return (SparcInstrSchedClass) si;
-// }
-//
-// inline operator const SparcInstrSchedClass (int i) {
-// return (const SparcInstrSchedClass) si;
-// }
//---------------------------------------------------------------------------
// enum SparcMachineOpCode.
@@ -60,7 +48,6 @@ enum SparcInstrSchedClass {
//
//---------------------------------------------------------------------------
-
enum SparcMachineOpCode {
NOP,
diff --git a/llvm/lib/Target/Sparc/SparcV9RegInfo.h b/llvm/lib/Target/Sparc/SparcV9RegInfo.h
index 3ebef550f08..67aa3a62ea3 100644
--- a/llvm/lib/Target/Sparc/SparcV9RegInfo.h
+++ b/llvm/lib/Target/Sparc/SparcV9RegInfo.h
@@ -7,7 +7,7 @@
#ifndef SPARC_INT_REG_CLASS_H
#define SPARC_INT_REG_CLASS_H
-#include "llvm/Target/Machine.h"
+#include "llvm/Target/RegInfo.h"
//-----------------------------------------------------------------------------
// Integer Register Class
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