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-rw-r--r--llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp45
-rw-r--r--llvm/lib/Target/Sparc/SparcTargetMachine.cpp58
-rw-r--r--llvm/lib/Target/Sparc/SparcTargetMachine.h16
3 files changed, 49 insertions, 70 deletions
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
index 889e2fd19ba..bd6596faee5 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
@@ -69,43 +69,6 @@ createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
}
-// Code models. Some only make sense for 64-bit code.
-//
-// SunCC Reloc CodeModel Constraints
-// abs32 Static Small text+data+bss linked below 2^32 bytes
-// abs44 Static Medium text+data+bss linked below 2^44 bytes
-// abs64 Static Large text smaller than 2^31 bytes
-// pic13 PIC_ Small GOT < 2^13 bytes
-// pic32 PIC_ Medium GOT < 2^32 bytes
-//
-// All code models require that the text segment is smaller than 2GB.
-
-static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
- CodeModel::Model &CM) {
- // The default 32-bit code model is abs32/pic32 and the default 32-bit
- // code model for JIT is abs32.
- switch (CM) {
- default: break;
- case CodeModel::Default:
- case CodeModel::JITDefault: CM = CodeModel::Small; break;
- }
-}
-
-static void adjustCodeGenOptsV9(const Triple &TT, Reloc::Model RM,
- CodeModel::Model &CM) {
- // The default 64-bit code model is abs44/pic32 and the default 64-bit
- // code model for JIT is abs64.
- switch (CM) {
- default: break;
- case CodeModel::Default:
- CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
- break;
- case CodeModel::JITDefault:
- CM = CodeModel::Large;
- break;
- }
-}
-
static MCTargetStreamer *
createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
return new SparcTargetELFStreamer(S);
@@ -159,12 +122,4 @@ extern "C" void LLVMInitializeSparcTargetMC() {
// Register the MCInstPrinter
TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter);
}
-
- // Register the MC codegen info.
- TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcTarget(),
- adjustCodeGenOpts);
- TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcV9Target(),
- adjustCodeGenOptsV9);
- TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcelTarget(),
- adjustCodeGenOpts);
}
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index a07bca1bd26..a0d40653fd9 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -60,15 +60,39 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
return *RM;
}
+// Code models. Some only make sense for 64-bit code.
+//
+// SunCC Reloc CodeModel Constraints
+// abs32 Static Small text+data+bss linked below 2^32 bytes
+// abs44 Static Medium text+data+bss linked below 2^44 bytes
+// abs64 Static Large text smaller than 2^31 bytes
+// pic13 PIC_ Small GOT < 2^13 bytes
+// pic32 PIC_ Medium GOT < 2^32 bytes
+//
+// All code models require that the text segment is smaller than 2GB.
+static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
+ Reloc::Model RM, bool Is64Bit,
+ bool JIT) {
+ if (CM)
+ return *CM;
+ if (Is64Bit) {
+ if (JIT)
+ return CodeModel::Large;
+ return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
+ }
+ return CodeModel::Small;
+}
+
/// Create an ILP32 architecture model
-SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
- StringRef CPU, StringRef FS,
- const TargetOptions &Options,
- Optional<Reloc::Model> RM,
- CodeModel::Model CM,
- CodeGenOpt::Level OL, bool is64bit)
- : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
- getEffectiveRelocModel(RM), CM, OL),
+SparcTargetMachine::SparcTargetMachine(
+ const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
+ const TargetOptions &Options, Optional<Reloc::Model> RM,
+ Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
+ : LLVMTargetMachine(
+ T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
+ getEffectiveRelocModel(RM),
+ getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT),
+ OL),
TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
initAsmInfo();
@@ -164,9 +188,9 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
- CodeModel::Model CM,
- CodeGenOpt::Level OL)
- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+ Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT)
+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
void SparcV9TargetMachine::anchor() { }
@@ -174,9 +198,9 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
- CodeModel::Model CM,
- CodeGenOpt::Level OL)
- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
+ Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT)
+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
void SparcelTargetMachine::anchor() {}
@@ -184,6 +208,6 @@ SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
- CodeModel::Model CM,
- CodeGenOpt::Level OL)
- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
+ Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT)
+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index faf714cbe2c..b0d76abeba7 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -28,8 +28,8 @@ class SparcTargetMachine : public LLVMTargetMachine {
public:
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
- Optional<Reloc::Model> RM, CodeModel::Model CM,
- CodeGenOpt::Level OL, bool is64bit);
+ Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT, bool is64bit);
~SparcTargetMachine() override;
const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; }
@@ -53,8 +53,8 @@ class SparcV8TargetMachine : public SparcTargetMachine {
public:
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
- Optional<Reloc::Model> RM, CodeModel::Model CM,
- CodeGenOpt::Level OL);
+ Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT);
};
/// Sparc 64-bit target machine
@@ -64,8 +64,8 @@ class SparcV9TargetMachine : public SparcTargetMachine {
public:
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
- Optional<Reloc::Model> RM, CodeModel::Model CM,
- CodeGenOpt::Level OL);
+ Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT);
};
class SparcelTargetMachine : public SparcTargetMachine {
@@ -74,8 +74,8 @@ class SparcelTargetMachine : public SparcTargetMachine {
public:
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options,
- Optional<Reloc::Model> RM, CodeModel::Model CM,
- CodeGenOpt::Level OL);
+ Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+ CodeGenOpt::Level OL, bool JIT);
};
} // end namespace llvm
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