diff options
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/EmitAssembly.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrSelection.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcRegInfo.cpp | 15 |
3 files changed, 9 insertions, 10 deletions
diff --git a/llvm/lib/Target/Sparc/EmitAssembly.cpp b/llvm/lib/Target/Sparc/EmitAssembly.cpp index caf9d45f304..68383c01107 100644 --- a/llvm/lib/Target/Sparc/EmitAssembly.cpp +++ b/llvm/lib/Target/Sparc/EmitAssembly.cpp @@ -382,7 +382,7 @@ SparcFunctionAsmPrinter::printOneOperand(const MachineOperand &mop) else needBitsFlag = false; - switch (mop.getOperandType()) + switch (mop.getType()) { case MachineOperand::MO_VirtualRegister: case MachineOperand::MO_CCRegister: diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp index 4a55df3407f..15d03a64ad9 100644 --- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp @@ -1106,7 +1106,7 @@ ForwardOperand(InstructionNode* treeNode, for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i) { const MachineOperand& mop = minstr->getOperand(i); - if (mop.getOperandType() == MachineOperand::MO_VirtualRegister && + if (mop.getType() == MachineOperand::MO_VirtualRegister && mop.getVRegValue() == unusedOp) minstr->SetMachineOperandVal(i, MachineOperand::MO_VirtualRegister, fwdOp); diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp index 17c210f74e4..e80185841f6 100644 --- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp @@ -1599,11 +1599,10 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec, // last operand is the def (unless for a store which has no def reg) MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1); - if( DefOp.opIsDef() && - DefOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (DefOp.opIsDef() && + DefOp.getType() == MachineOperand::MO_MachineRegister) { // If the operand in DefInst is a def ... - bool DefEqUse = false; std::vector<MachineInstr *>::iterator UseIt = DefIt; @@ -1617,8 +1616,8 @@ void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec, // for each inst (UseInst) that is below the DefInst do ... MachineOperand& UseOp = UseInst->getOperand(0); - if( ! UseOp.opIsDef() && - UseOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (!UseOp.opIsDef() && + UseOp.getType() == MachineOperand::MO_MachineRegister) { // if use is a register ... @@ -1678,8 +1677,8 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec, PhyRegAlloc &PRA) const { MachineOperand& UseOp = UnordInst->getOperand(0); - if( ! UseOp.opIsDef() && - UseOp.getOperandType() == MachineOperand::MO_MachineRegister) { + if (!UseOp.opIsDef() && + UseOp.getType() == MachineOperand::MO_MachineRegister) { // for the use of UnordInst, see whether there is a defining instr // before in the OrdVec @@ -1695,7 +1694,7 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec, OrdInst->getOperand(OrdInst->getNumOperands()-1); if( DefOp.opIsDef() && - DefOp.getOperandType() == MachineOperand::MO_MachineRegister) { + DefOp.getType() == MachineOperand::MO_MachineRegister) { //cerr << "\nDefining Ord Inst: " << *OrdInst; |
