diff options
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcTargetMachine.cpp')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index cf634d13dac..7834fb279a0 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -53,15 +53,22 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) { return Ret; } +static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { + if (!RM.hasValue()) + return Reloc::Static; + return *RM; +} + /// Create an ILP32 architecture model /// SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, - RM, CM, OL), + getEffectiveRelocModel(RM), CM, OL), TLOF(make_unique<SparcELFTargetObjectFile>()) { initAsmInfo(); this->is64Bit = is64bit; @@ -144,7 +151,8 @@ void SparcV8TargetMachine::anchor() { } SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} @@ -153,7 +161,8 @@ void SparcV9TargetMachine::anchor() { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} @@ -162,6 +171,7 @@ void SparcelTargetMachine::anchor() {} SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, + CodeModel::Model CM, CodeGenOpt::Level OL) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} |