diff options
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.td | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index a9bd0ff5336..3f64ef0bac8 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1505,7 +1505,7 @@ let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in IntRegs:$swap), "cas [$rs1], $rs2, $rd", [(set i32:$rd, - (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>; + (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; // CASA is supported as an instruction on some LEON3 and all LEON4 processors. @@ -1516,7 +1516,7 @@ let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in IntRegs:$swap), "casa [$rs1] 10, $rs2, $rd", [(set i32:$rd, - (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>; + (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; // CASA supported on some LEON3 and all LEON4 processors. Same pattern as // CASrr, above, but with a different ASI. This version is supported for @@ -1645,13 +1645,21 @@ def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; let Predicates = [HasNoV9] in def : Pat<(atomic_fence imm, imm), (STBAR)>; -// atomic_load_32 addr -> load addr -def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>; -def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>; - -// atomic_store_32 val, addr -> store val, addr -def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>; -def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; +// atomic_load addr -> load addr +def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; +def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>; +def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; +def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>; +def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>; +def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>; + +// atomic_store val, addr -> store val, addr +def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>; +def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>; +def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>; +def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>; +def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>; +def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; // extract_vector def : Pat<(extractelt (v2i32 IntPair:$Rn), 0), |
