1 files changed, 58 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index b1dd9e67655..76c3d559c70 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -37,6 +37,13 @@ def uimm8_lsb000 : Operand<XLenVT>,
   let DecoderMethod = "decodeUImmOperand<8>";
 }
 
+// A 9-bit signed immediate where the least significant bit is zero.
+def simm9_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
+}
+
 // A 9-bit unsigned immediate where the least significant three bits are zero.
 def uimm9_lsb000 : Operand<XLenVT>,
                    ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
@@ -45,6 +52,13 @@ def uimm9_lsb000 : Operand<XLenVT>,
   let DecoderMethod = "decodeUImmOperand<9>";
 }
 
+// A 12-bit signed immediate where the least significant bit is zero.
+def simm12_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
@@ -73,6 +87,20 @@ class CStore_rri<bits<3> funct3, string OpcodeStr,
       RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, cls:$rs1, opnd:$imm),
                  OpcodeStr, "$rs2, ${imm}(${rs1})">;
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Bcz<bits<3> funct3, string OpcodeStr, PatFrag CondOp,
+          RegisterClass cls> :
+      RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
+                 OpcodeStr, "$rs1, $imm"> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let Inst{12} = imm{7};
+  let Inst{11-10} = imm{3-2};
+  let Inst{6-5} = imm{6-5};
+  let Inst{4-3} = imm{1-0};
+  let Inst{2} = imm{4};
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -107,6 +135,21 @@ def CSD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
   let Inst{6-5} = imm{7-6};
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1 in
+def CJAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
+                      "c.jal", "$offset">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def CJ : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
+                    "c.j", "$offset"> {
+  let isBranch = 1;
+  let isTerminator=1;
+  let isBarrier=1;
+}
+
+def CBEQZ : Bcz<0b110, "c.beqz",  seteq, GPRC>;
+def CBNEZ : Bcz<0b111, "c.bnez",  setne, GPRC>;
+
 def CLWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00> {
   let Inst{6-4} = imm{4-2};
   let Inst{3-2} = imm{7-6};
@@ -118,6 +161,21 @@ def CLDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
   let Inst{4-2} = imm{8-6};
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def CJR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
+                     "c.jr", "$rs1"> {
+  let isBranch = 1;
+  let isBarrier = 1;
+  let isTerminator = 1;
+  let isIndirectBranch = 1;
+  let rs2 = 0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    isCall=1, Defs=[X1], rs2 = 0 in
+def CJALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
+                       "c.jalr", "$rs1">;
+
 def CSWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00> {
   let Inst{12-9} = imm{5-2};
   let Inst{8-7}  = imm{7-6};