diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 27 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 40 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 32 |
3 files changed, 49 insertions, 50 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 9624e66be8e..900dd3cdc9f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -311,7 +311,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { static bool isFloatingPointZero(SDOperand Op) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); - else if (ISD::isEXTLoad(Op.Val) || Op.getOpcode() == ISD::LOAD) { + else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { // Maybe this has already been legalized into the constant pool? if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) @@ -694,7 +694,7 @@ static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { // If the global is weak or external, we have to go through the lazy // resolution stub. - return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); + return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); } static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { @@ -873,8 +873,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset); SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); - ArgVal = DAG.getLoad(ObjectVT, Root, FIN, - DAG.getSrcValue(NULL)); + ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); } else { // Don't emit a dead load. ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); @@ -1051,16 +1050,14 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { // Float varargs are always shadowed in available integer registers if (GPR_idx != NumGPRs) { - SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, - DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) { SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, - DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } @@ -1401,7 +1398,7 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { DAG.getEntryNode(), Ext64, FIdx, DAG.getSrcValue(NULL)); // Load the value as a double. - SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); + SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); // FCFID it and return it. SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); @@ -2124,7 +2121,7 @@ static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { SDOperand Store = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); // Load it out. - return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); + return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); } static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { @@ -2383,18 +2380,20 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, break; case ISD::BSWAP: // Turn BSWAP (LOAD) -> lhbrx/lwbrx. - if (N->getOperand(0).getOpcode() == ISD::LOAD && + if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && N->getOperand(0).hasOneUse() && (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { SDOperand Load = N->getOperand(0); + LoadSDNode *LD = cast<LoadSDNode>(Load); // Create the byte-swapping load. std::vector<MVT::ValueType> VTs; VTs.push_back(MVT::i32); VTs.push_back(MVT::Other); + SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset()); SDOperand Ops[] = { - Load.getOperand(0), // Chain - Load.getOperand(1), // Ptr - Load.getOperand(2), // SrcValue + LD->getChain(), // Chain + LD->getBasePtr(), // Ptr + SV, // SrcValue DAG.getValueType(N->getValueType(0)) // VT }; SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index d822c66ead6..762a754b4e2 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -233,41 +233,41 @@ let isLoad = 1, PPC970_Unit = 2 in { // Sign extending loads. def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src), "lha $rD, $src", LdStLHA, - [(set G8RC:$rD, (sextload iaddr:$src, i16))]>, + [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src), "lwa $rD, $src", LdStLWA, - [(set G8RC:$rD, (sextload ixaddr:$src, i32))]>, isPPC64, + [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src), "lhax $rD, $src", LdStLHA, - [(set G8RC:$rD, (sextload xaddr:$src, i16))]>, + [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), "lwax $rD, $src", LdStLHA, - [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64, + [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, PPC970_DGroup_Cracked; // Zero extending loads. def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src), "lbz $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload iaddr:$src, i8))]>; + [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src), "lhz $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload iaddr:$src, i16))]>; + [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src), "lwz $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload iaddr:$src, i32))]>, isPPC64; + [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src), "lbzx $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload xaddr:$src, i8))]>; + [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src), "lhzx $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload xaddr:$src, i16))]>; + [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src), "lwzx $rD, $src", LdStGeneral, - [(set G8RC:$rD, (zextload xaddr:$src, i32))]>; + [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; // Full 8-byte loads. @@ -397,25 +397,25 @@ def : Pat<(i32 (trunc G8RC:$in)), (OR8To4 G8RC:$in, G8RC:$in)>; // Extending loads with i64 targets. -def : Pat<(zextload iaddr:$src, i1), +def : Pat<(zextloadi1 iaddr:$src), (LBZ8 iaddr:$src)>; -def : Pat<(zextload xaddr:$src, i1), +def : Pat<(zextloadi1 xaddr:$src), (LBZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i1), +def : Pat<(extloadi1 iaddr:$src), (LBZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i1), +def : Pat<(extloadi1 xaddr:$src), (LBZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i8), +def : Pat<(extloadi8 iaddr:$src), (LBZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i8), +def : Pat<(extloadi8 xaddr:$src), (LBZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i16), +def : Pat<(extloadi16 iaddr:$src), (LHZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i16), +def : Pat<(extloadi16 xaddr:$src), (LHZX8 xaddr:$src)>; -def : Pat<(extload iaddr:$src, i32), +def : Pat<(extloadi32 iaddr:$src), (LWZ8 iaddr:$src)>; -def : Pat<(extload xaddr:$src, i32), +def : Pat<(extloadi32 xaddr:$src), (LWZX8 xaddr:$src)>; // SHL/SRL diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 4c6b36b6804..f346717a3d7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -379,14 +379,14 @@ def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst), let isLoad = 1, PPC970_Unit = 2 in { def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src), "lbz $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload iaddr:$src, i8))]>; + [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src), "lha $rD, $src", LdStLHA, - [(set GPRC:$rD, (sextload iaddr:$src, i16))]>, + [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, PPC970_DGroup_Cracked; def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src), "lhz $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload iaddr:$src, i16))]>; + [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src), "lwz $rD, $src", LdStGeneral, [(set GPRC:$rD, (load iaddr:$src))]>; @@ -490,14 +490,14 @@ def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst), let isLoad = 1, PPC970_Unit = 2 in { def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src), "lbzx $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload xaddr:$src, i8))]>; + [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src), "lhax $rD, $src", LdStLHA, - [(set GPRC:$rD, (sextload xaddr:$src, i16))]>, + [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, PPC970_DGroup_Cracked; def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src), "lhzx $rD, $src", LdStGeneral, - [(set GPRC:$rD, (zextload xaddr:$src, i16))]>; + [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src), "lwzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (load xaddr:$src))]>; @@ -990,25 +990,25 @@ def : Pat<(srl GPRC:$rS, GPRC:$rB), def : Pat<(shl GPRC:$rS, GPRC:$rB), (SLW GPRC:$rS, GPRC:$rB)>; -def : Pat<(zextload iaddr:$src, i1), +def : Pat<(zextloadi1 iaddr:$src), (LBZ iaddr:$src)>; -def : Pat<(zextload xaddr:$src, i1), +def : Pat<(zextloadi1 xaddr:$src), (LBZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, i1), +def : Pat<(extloadi1 iaddr:$src), (LBZ iaddr:$src)>; -def : Pat<(extload xaddr:$src, i1), +def : Pat<(extloadi1 xaddr:$src), (LBZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, i8), +def : Pat<(extloadi8 iaddr:$src), (LBZ iaddr:$src)>; -def : Pat<(extload xaddr:$src, i8), +def : Pat<(extloadi8 xaddr:$src), (LBZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, i16), +def : Pat<(extloadi16 iaddr:$src), (LHZ iaddr:$src)>; -def : Pat<(extload xaddr:$src, i16), +def : Pat<(extloadi16 xaddr:$src), (LHZX xaddr:$src)>; -def : Pat<(extload iaddr:$src, f32), +def : Pat<(extloadf32 iaddr:$src), (FMRSD (LFS iaddr:$src))>; -def : Pat<(extload xaddr:$src, f32), +def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; include "PPCInstrAltivec.td" |
