diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp | 38 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 40 |
4 files changed, 45 insertions, 45 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp index 2af1913db55..4c101f58601 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp @@ -62,11 +62,11 @@ namespace llvm { /// BB#0: derived from LLVM BB %entry /// Live Ins: %f1 %f3 %x6 /// <SNIP1> -/// %vreg0<def> = COPY %f1; F8RC:%vreg0 -/// %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4 -/// %vreg8<def> = LXSDX %zero8, %vreg7<kill>, %rm<imp-use>; -/// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7 -/// BCC 76, %vreg5, <BB#2>; CRRC:%vreg5 +/// %0<def> = COPY %f1; F8RC:%0 +/// %5<def> = CMPLWI %4<kill>, 0; CRRC:%5 GPRC:%4 +/// %8<def> = LXSDX %zero8, %7<kill>, %rm<imp-use>; +/// mem:LD8[ConstantPool] F8RC:%8 G8RC:%7 +/// BCC 76, %5, <BB#2>; CRRC:%5 /// Successors according to CFG: BB#1(?%) BB#2(?%) /// /// BB#1: derived from LLVM BB %entry @@ -75,10 +75,10 @@ namespace llvm { /// /// BB#2: derived from LLVM BB %entry /// Predecessors according to CFG: BB#0 BB#1 -/// %vreg9<def> = PHI %vreg8, <BB#1>, %vreg0, <BB#0>; -/// F8RC:%vreg9,%vreg8,%vreg0 +/// %9<def> = PHI %8, <BB#1>, %0, <BB#0>; +/// F8RC:%9,%8,%0 /// <SNIP2> -/// BCC 76, %vreg5, <BB#4>; CRRC:%vreg5 +/// BCC 76, %5, <BB#4>; CRRC:%5 /// Successors according to CFG: BB#3(?%) BB#4(?%) /// /// BB#3: derived from LLVM BB %entry @@ -87,8 +87,8 @@ namespace llvm { /// /// BB#4: derived from LLVM BB %entry /// Predecessors according to CFG: BB#2 BB#3 -/// %vreg13<def> = PHI %vreg12, <BB#3>, %vreg2, <BB#2>; -/// F8RC:%vreg13,%vreg12,%vreg2 +/// %13<def> = PHI %12, <BB#3>, %2, <BB#2>; +/// F8RC:%13,%12,%2 /// <SNIP3> /// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use> /// @@ -100,12 +100,12 @@ namespace llvm { /// BB#0: derived from LLVM BB %entry /// Live Ins: %f1 %f3 %x6 /// <SNIP1> -/// %vreg0<def> = COPY %f1; F8RC:%vreg0 -/// %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4 -/// %vreg8<def> = LXSDX %zero8, %vreg7<kill>, %rm<imp-use>; -/// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7 +/// %0<def> = COPY %f1; F8RC:%0 +/// %5<def> = CMPLWI %4<kill>, 0; CRRC:%5 GPRC:%4 +/// %8<def> = LXSDX %zero8, %7<kill>, %rm<imp-use>; +/// mem:LD8[ConstantPool] F8RC:%8 G8RC:%7 /// <SNIP2> -/// BCC 76, %vreg5, <BB#4>; CRRC:%vreg5 +/// BCC 76, %5, <BB#4>; CRRC:%5 /// Successors according to CFG: BB#1(0x2aaaaaaa / 0x80000000 = 33.33%) /// BB#4(0x55555554 / 0x80000000 = 66.67%) /// @@ -115,10 +115,10 @@ namespace llvm { /// /// BB#4: derived from LLVM BB %entry /// Predecessors according to CFG: BB#0 BB#1 -/// %vreg9<def> = PHI %vreg8, <BB#1>, %vreg0, <BB#0>; -/// F8RC:%vreg9,%vreg8,%vreg0 -/// %vreg13<def> = PHI %vreg12, <BB#1>, %vreg2, <BB#0>; -/// F8RC:%vreg13,%vreg12,%vreg2 +/// %9<def> = PHI %8, <BB#1>, %0, <BB#0>; +/// F8RC:%9,%8,%0 +/// %13<def> = PHI %12, <BB#1>, %2, <BB#0>; +/// F8RC:%13,%12,%2 /// <SNIP3> /// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use> /// diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index fd566634760..15cc1c76760 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2318,7 +2318,7 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, // ADJCALLSTACKDOWN 32, %r1<imp-def,dead>, %r1<imp-use> // BL8_NOP <ga:@func>,... // ADJCALLSTACKUP 32, 0, %r1<imp-def,dead>, %r1<imp-use> - // %vreg5<def> = COPY %x3; G8RC:%vreg5 + // %5<def> = COPY %x3; G8RC:%5 if (SrcReg == PPC::X3) { const MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock::const_instr_iterator II = diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index a8d98133afc..1ac7afe2cdc 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -585,9 +585,9 @@ bool PPCMIPeephole::simplifyCode(void) { // We can eliminate RLDICL (e.g. for zero-extension) // if all bits to clear are already zero in the input. // This code assume following code sequence for zero-extension. - // %vreg6<def> = COPY %vreg5:sub_32; (optional) - // %vreg8<def> = IMPLICIT_DEF; - // %vreg7<def,tied1> = INSERT_SUBREG %vreg8<tied0>, %vreg6, sub_32; + // %6<def> = COPY %5:sub_32; (optional) + // %8<def> = IMPLICIT_DEF; + // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32; if (!EnableZExtElimination) break; if (MI.getOperand(2).getImm() != 0) @@ -685,8 +685,8 @@ bool PPCMIPeephole::simplifyCode(void) { DEBUG(dbgs() << "Optimizing LI to ADDI: "); DEBUG(LiMI->dump()); - // There could be repeated registers in the PHI, e.g: %vreg1<def> = - // PHI %vreg6, <BB#2>, %vreg8, <BB#3>, %vreg8, <BB#6>; So if we've + // There could be repeated registers in the PHI, e.g: %1<def> = + // PHI %6, <BB#2>, %8, <BB#3>, %8, <BB#6>; So if we've // already replaced the def instruction, skip. if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) continue; diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index 80b63b1c9df..4d001c0210d 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -90,21 +90,21 @@ protected: // This pass is run after register coalescing, and so we're looking for // a situation like this: // ... - // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 - // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, - // %rm<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 + // %5<def> = COPY %9; VSLRC:%5,%9 + // %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16, + // %rm<imp-use>; VSLRC:%5,%17,%16 // ... - // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19, - // %rm<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19 + // %9<def,tied1> = XSMADDADP %9<tied0>, %17, %19, + // %rm<imp-use>; VSLRC:%9,%17,%19 // ... // Where we can eliminate the copy by changing from the A-type to the // M-type instruction. Specifically, for this example, this means: - // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, - // %rm<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 + // %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16, + // %rm<imp-use>; VSLRC:%5,%17,%16 // is replaced by: - // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9, - // %rm<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9 - // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 + // %16<def,tied1> = XSMADDMDP %16<tied0>, %18, %9, + // %rm<imp-use>; VSLRC:%16,%18,%9 + // and we remove: %5<def> = COPY %9; VSLRC:%5,%9 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); @@ -150,13 +150,13 @@ protected: // walking the MIs we may as well test liveness here. // // FIXME: There is a case that occurs in practice, like this: - // %vreg9<def> = COPY %f1; VSSRC:%vreg9 + // %9<def> = COPY %f1; VSSRC:%9 // ... - // %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9 - // %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9 - // %vreg9<def,tied1> = XSMADDASP %vreg9<tied0>, %vreg1, %vreg4; VSSRC: - // %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg1, %vreg2; VSSRC: - // %vreg7<def,tied1> = XSMADDASP %vreg7<tied0>, %vreg1, %vreg3; VSSRC: + // %6<def> = COPY %9; VSSRC:%6,%9 + // %7<def> = COPY %9; VSSRC:%7,%9 + // %9<def,tied1> = XSMADDASP %9<tied0>, %1, %4; VSSRC: + // %6<def,tied1> = XSMADDASP %6<tied0>, %1, %2; VSSRC: + // %7<def,tied1> = XSMADDASP %7<tied0>, %1, %3; VSSRC: // which prevents an otherwise-profitable transformation. bool OtherUsers = false, KillsAddendSrc = false; for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI); @@ -177,11 +177,11 @@ protected: // The transformation doesn't work well with things like: - // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5; - // unless vreg11 is also a kill, so skip when it is not, + // %5 = A-form-op %5, %11, %5; + // unless %11 is also a kill, so skip when it is not, // and check operand 3 to see it is also a kill to handle the case: - // %vreg5 = A-form-op %vreg5, %vreg5, %vreg11; - // where vreg5 and vreg11 are both kills. This case would be skipped + // %5 = A-form-op %5, %5, %11; + // where %5 and %11 are both kills. This case would be skipped // otherwise. unsigned OldFMAReg = MI.getOperand(0).getReg(); |
