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-rw-r--r--llvm/lib/Target/PowerPC/PPCScheduleA2.td224
1 files changed, 112 insertions, 112 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
index 324a0bfd982..0dadcd65314 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
@@ -25,118 +25,118 @@ def FU : FuncUnit; // FI pipeline
def PPCA2Itineraries : ProcessorItineraries<
[XU, FU], [], [
- InstrItinData<IntSimple , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<IntGeneral , [InstrStage<1, [XU]>],
- [2, 1, 1]>,
- InstrItinData<IntCompare , [InstrStage<1, [XU]>],
- [2, 1, 1]>,
- InstrItinData<IntDivW , [InstrStage<1, [XU]>],
- [39, 1, 1]>,
- InstrItinData<IntDivD , [InstrStage<1, [XU]>],
- [71, 1, 1]>,
- InstrItinData<IntMulHW , [InstrStage<1, [XU]>],
- [5, 1, 1]>,
- InstrItinData<IntMulHWU , [InstrStage<1, [XU]>],
- [5, 1, 1]>,
- InstrItinData<IntMulLI , [InstrStage<1, [XU]>],
- [6, 1, 1]>,
- InstrItinData<IntRotate , [InstrStage<1, [XU]>],
- [2, 1, 1]>,
- InstrItinData<IntRotateD , [InstrStage<1, [XU]>],
- [2, 1, 1]>,
- InstrItinData<IntRotateDI , [InstrStage<1, [XU]>],
- [2, 1, 1]>,
- InstrItinData<IntShift , [InstrStage<1, [XU]>],
- [2, 1, 1]>,
- InstrItinData<IntTrapW , [InstrStage<1, [XU]>],
- [2, 1]>,
- InstrItinData<IntTrapD , [InstrStage<1, [XU]>],
- [2, 1]>,
- InstrItinData<BrB , [InstrStage<1, [XU]>],
- [6, 1, 1]>,
- InstrItinData<BrCR , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<BrMCR , [InstrStage<1, [XU]>],
- [5, 1, 1]>,
- InstrItinData<BrMCRX , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStDCBA , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStDCBF , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStDCBI , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStLoad , [InstrStage<1, [XU]>],
- [6, 1, 1]>,
- InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>],
- [6, 8, 1, 1]>,
- InstrItinData<LdStLDU , [InstrStage<1, [XU]>],
- [6, 1, 1]>,
- InstrItinData<LdStStore , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStStoreUpd, [InstrStage<1, [XU]>],
- [2, 1, 1, 1]>,
- InstrItinData<LdStICBI, [InstrStage<1, [XU]>],
- [16, 1, 1]>,
- InstrItinData<LdStSTFD , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStSTFDU , [InstrStage<1, [XU]>],
- [2, 1, 1, 1]>,
- InstrItinData<LdStLFD , [InstrStage<1, [XU]>],
- [7, 1, 1]>,
- InstrItinData<LdStLFDU , [InstrStage<1, [XU]>],
- [7, 9, 1, 1]>,
- InstrItinData<LdStLHA , [InstrStage<1, [XU]>],
- [6, 1, 1]>,
- InstrItinData<LdStLHAU , [InstrStage<1, [XU]>],
- [6, 8, 1, 1]>,
- InstrItinData<LdStLWARX , [InstrStage<1, [XU]>],
- [82, 1, 1]>, // L2 latency
- InstrItinData<LdStSTD , [InstrStage<1, [XU]>],
- [1, 1, 1]>,
- InstrItinData<LdStSTDU , [InstrStage<1, [XU]>],
- [2, 1, 1, 1]>,
- InstrItinData<LdStSTDCX , [InstrStage<1, [XU]>],
- [82, 1, 1]>, // L2 latency
- InstrItinData<LdStSTWCX , [InstrStage<1, [XU]>],
- [82, 1, 1]>, // L2 latency
- InstrItinData<LdStSync , [InstrStage<1, [XU]>],
- [6]>,
- InstrItinData<SprISYNC , [InstrStage<1, [XU]>],
- [16]>,
- InstrItinData<SprMTMSR , [InstrStage<1, [XU]>],
- [16, 1]>,
- InstrItinData<SprMFCR , [InstrStage<1, [XU]>],
- [6, 1]>,
- InstrItinData<SprMFMSR , [InstrStage<1, [XU]>],
- [4, 1]>,
- InstrItinData<SprMFSPR , [InstrStage<1, [XU]>],
- [6, 1]>,
- InstrItinData<SprMFTB , [InstrStage<1, [XU]>],
- [4, 1]>,
- InstrItinData<SprMTSPR , [InstrStage<1, [XU]>],
- [6, 1]>,
- InstrItinData<SprRFI , [InstrStage<1, [XU]>],
- [16]>,
- InstrItinData<SprSC , [InstrStage<1, [XU]>],
- [16]>,
- InstrItinData<FPGeneral , [InstrStage<1, [FU]>],
- [6, 1, 1]>,
- InstrItinData<FPAddSub , [InstrStage<1, [FU]>],
- [6, 1, 1]>,
- InstrItinData<FPCompare , [InstrStage<1, [FU]>],
- [5, 1, 1]>,
- InstrItinData<FPDivD , [InstrStage<1, [FU]>],
- [72, 1, 1]>,
- InstrItinData<FPDivS , [InstrStage<1, [FU]>],
- [59, 1, 1]>,
- InstrItinData<FPSqrt , [InstrStage<1, [FU]>],
- [69, 1, 1]>,
- InstrItinData<FPFused , [InstrStage<1, [FU]>],
- [6, 1, 1, 1]>,
- InstrItinData<FPRes , [InstrStage<1, [FU]>],
- [6, 1]>
+ InstrItinData<IIC_IntSimple, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_IntGeneral, [InstrStage<1, [XU]>],
+ [2, 1, 1]>,
+ InstrItinData<IIC_IntCompare, [InstrStage<1, [XU]>],
+ [2, 1, 1]>,
+ InstrItinData<IIC_IntDivW, [InstrStage<1, [XU]>],
+ [39, 1, 1]>,
+ InstrItinData<IIC_IntDivD, [InstrStage<1, [XU]>],
+ [71, 1, 1]>,
+ InstrItinData<IIC_IntMulHW, [InstrStage<1, [XU]>],
+ [5, 1, 1]>,
+ InstrItinData<IIC_IntMulHWU, [InstrStage<1, [XU]>],
+ [5, 1, 1]>,
+ InstrItinData<IIC_IntMulLI, [InstrStage<1, [XU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_IntRotate, [InstrStage<1, [XU]>],
+ [2, 1, 1]>,
+ InstrItinData<IIC_IntRotateD, [InstrStage<1, [XU]>],
+ [2, 1, 1]>,
+ InstrItinData<IIC_IntRotateDI, [InstrStage<1, [XU]>],
+ [2, 1, 1]>,
+ InstrItinData<IIC_IntShift, [InstrStage<1, [XU]>],
+ [2, 1, 1]>,
+ InstrItinData<IIC_IntTrapW, [InstrStage<1, [XU]>],
+ [2, 1]>,
+ InstrItinData<IIC_IntTrapD, [InstrStage<1, [XU]>],
+ [2, 1]>,
+ InstrItinData<IIC_BrB, [InstrStage<1, [XU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_BrCR, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_BrMCR, [InstrStage<1, [XU]>],
+ [5, 1, 1]>,
+ InstrItinData<IIC_BrMCRX, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStDCBA, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStDCBF, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStDCBI, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStLoad, [InstrStage<1, [XU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [XU]>],
+ [6, 8, 1, 1]>,
+ InstrItinData<IIC_LdStLDU, [InstrStage<1, [XU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_LdStStore, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [XU]>],
+ [2, 1, 1, 1]>,
+ InstrItinData<IIC_LdStICBI, [InstrStage<1, [XU]>],
+ [16, 1, 1]>,
+ InstrItinData<IIC_LdStSTFD, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [XU]>],
+ [2, 1, 1, 1]>,
+ InstrItinData<IIC_LdStLFD, [InstrStage<1, [XU]>],
+ [7, 1, 1]>,
+ InstrItinData<IIC_LdStLFDU, [InstrStage<1, [XU]>],
+ [7, 9, 1, 1]>,
+ InstrItinData<IIC_LdStLHA, [InstrStage<1, [XU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_LdStLHAU, [InstrStage<1, [XU]>],
+ [6, 8, 1, 1]>,
+ InstrItinData<IIC_LdStLWARX, [InstrStage<1, [XU]>],
+ [82, 1, 1]>, // L2 latency
+ InstrItinData<IIC_LdStSTD, [InstrStage<1, [XU]>],
+ [1, 1, 1]>,
+ InstrItinData<IIC_LdStSTDU, [InstrStage<1, [XU]>],
+ [2, 1, 1, 1]>,
+ InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [XU]>],
+ [82, 1, 1]>, // L2 latency
+ InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [XU]>],
+ [82, 1, 1]>, // L2 latency
+ InstrItinData<IIC_LdStSync, [InstrStage<1, [XU]>],
+ [6]>,
+ InstrItinData<IIC_SprISYNC, [InstrStage<1, [XU]>],
+ [16]>,
+ InstrItinData<IIC_SprMTMSR, [InstrStage<1, [XU]>],
+ [16, 1]>,
+ InstrItinData<IIC_SprMFCR, [InstrStage<1, [XU]>],
+ [6, 1]>,
+ InstrItinData<IIC_SprMFMSR, [InstrStage<1, [XU]>],
+ [4, 1]>,
+ InstrItinData<IIC_SprMFSPR, [InstrStage<1, [XU]>],
+ [6, 1]>,
+ InstrItinData<IIC_SprMFTB, [InstrStage<1, [XU]>],
+ [4, 1]>,
+ InstrItinData<IIC_SprMTSPR, [InstrStage<1, [XU]>],
+ [6, 1]>,
+ InstrItinData<IIC_SprRFI, [InstrStage<1, [XU]>],
+ [16]>,
+ InstrItinData<IIC_SprSC, [InstrStage<1, [XU]>],
+ [16]>,
+ InstrItinData<IIC_FPGeneral, [InstrStage<1, [FU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_FPAddSub, [InstrStage<1, [FU]>],
+ [6, 1, 1]>,
+ InstrItinData<IIC_FPCompare, [InstrStage<1, [FU]>],
+ [5, 1, 1]>,
+ InstrItinData<IIC_FPDivD, [InstrStage<1, [FU]>],
+ [72, 1, 1]>,
+ InstrItinData<IIC_FPDivS, [InstrStage<1, [FU]>],
+ [59, 1, 1]>,
+ InstrItinData<IIC_FPSqrt, [InstrStage<1, [FU]>],
+ [69, 1, 1]>,
+ InstrItinData<IIC_FPFused, [InstrStage<1, [FU]>],
+ [6, 1, 1, 1]>,
+ InstrItinData<IIC_FPRes, [InstrStage<1, [FU]>],
+ [6, 1]>
]>;
// ===---------------------------------------------------------------------===//
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