diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 30f4e9bd2f5..881b17afcf1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -15,12 +15,25 @@ include "PPCInstrFormats.td" //===----------------------------------------------------------------------===// +// PowerPC specific type constraints. +// +def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx + SDTCisVT<0, f64>, SDTCisPtrTy<1> +]>; +def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl + SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> +]>; +def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; +def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>; + +//===----------------------------------------------------------------------===// // PowerPC specific DAG Nodes. // def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; +def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>; def PPCfsel : SDNode<"PPCISD::FSEL", // Type constraint for fsel. @@ -34,19 +47,14 @@ def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift // amounts. These nodes are generated by the multi-precision shift code. -def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl - SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32> -]>; def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>; def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>; def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>; // These are target-independent nodes, but have target-specific formats. -def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>; def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>; -def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>; def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, [SDNPHasChain, SDNPOptInFlag]>; @@ -636,9 +644,9 @@ def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB), let isStore = 1, noResults = 1 in { -def STFIWX: XForm_28<31, 983, (ops F4RC:$frS, memrr:$dst), +def STFIWX: XForm_28<31, 983, (ops F8RC:$frS, memrr:$dst), "stfiwx $frS, $dst", LdStUX, - []>; + [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst), "stfsx $frS, $dst", LdStUX, [(store F4RC:$frS, xaddr:$dst)]>; |
