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-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d203404659e..614f368f557 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3175,7 +3175,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
};
const unsigned Num_GPR_Regs = array_lengthof(GPR);
- const unsigned Num_FPR_Regs = 13;
+ const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
const unsigned Num_VR_Regs = array_lengthof(VR);
const unsigned Num_QFPR_Regs = Num_FPR_Regs;
@@ -3588,7 +3588,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
};
const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
- const unsigned Num_FPR_Regs = 13;
+ const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
const unsigned Num_VR_Regs = array_lengthof( VR);
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
@@ -10564,7 +10564,7 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
N->getOpcode() == ISD::UINT_TO_FP) &&
"Need an int -> FP conversion node here");
- if (!Subtarget.has64BitSupport())
+ if (useSoftFloat() || !Subtarget.has64BitSupport())
return SDValue();
SelectionDAG &DAG = DCI.DAG;
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