diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index e1f3ec21444..b1ab405e54f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1118,8 +1118,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setTargetDAGCombine(ISD::ANY_EXTEND); setTargetDAGCombine(ISD::TRUNCATE); - setTargetDAGCombine(ISD::VECTOR_SHUFFLE); - if (Subtarget.useCRBits()) { setTargetDAGCombine(ISD::TRUNCATE); @@ -1354,8 +1352,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { case PPCISD::SExtVElems: return "PPCISD::SExtVElems"; case PPCISD::LXVD2X: return "PPCISD::LXVD2X"; case PPCISD::STXVD2X: return "PPCISD::STXVD2X"; - case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE"; - case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE"; case PPCISD::ST_VSR_SCAL_INT: return "PPCISD::ST_VSR_SCAL_INT"; case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; @@ -13117,60 +13113,6 @@ SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N, return Val; } -SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN, - LSBaseSDNode *LSBase, - DAGCombinerInfo &DCI) const { - assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) && - "Not a reverse memop pattern!"); - - auto IsElementReverse = [](const ShuffleVectorSDNode *SVN) -> bool { - auto Mask = SVN->getMask(); - int i = 0; - auto I = Mask.rbegin(); - auto E = Mask.rend(); - - for (; I != E; ++I) { - if (*I != i) - return false; - i++; - } - return true; - }; - - SelectionDAG &DAG = DCI.DAG; - EVT VT = SVN->getValueType(0); - - if (!isTypeLegal(VT) || !Subtarget.isLittleEndian() || !Subtarget.hasVSX()) - return SDValue(); - - // Before P9, we don't have vector load/store instrs in big-endian - // element order for v8i16 or v16i8 - if (!Subtarget.hasP9Vector() && (VT == MVT::v8i16 || VT == MVT::v16i8)) - return SDValue(); - - if(!IsElementReverse(SVN)) - return SDValue(); - - if (LSBase->getOpcode() == ISD::LOAD) { - SDLoc dl(SVN); - SDValue LoadOps[] = {LSBase->getChain(), LSBase->getBasePtr()}; - return DAG.getMemIntrinsicNode( - PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps, - LSBase->getMemoryVT(), LSBase->getMemOperand()); - } - - if (LSBase->getOpcode() == ISD::STORE) { - SDLoc dl(LSBase); - SDValue StoreOps[] = {LSBase->getChain(), SVN->getOperand(0), - LSBase->getBasePtr()}; - return DAG.getMemIntrinsicNode( - PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps, - LSBase->getMemoryVT(), LSBase->getMemOperand()); - } - - llvm_unreachable("Expected a load or store node here"); -} - SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -13217,12 +13159,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: return combineFPToIntToFP(N, DCI); - case ISD::VECTOR_SHUFFLE: - if (ISD::isNormalLoad(N->getOperand(0).getNode())) { - LSBaseSDNode* LSBase = cast<LSBaseSDNode>(N->getOperand(0)); - return combineVReverseMemOP(cast<ShuffleVectorSDNode>(N), LSBase, DCI); - } - break; case ISD::STORE: { EVT Op1VT = N->getOperand(1).getValueType(); @@ -13234,13 +13170,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, return Val; } - if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) { - ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N->getOperand(1)); - SDValue Val= combineVReverseMemOP(SVN, cast<LSBaseSDNode>(N), DCI); - if (Val) - return Val; - } - // Turn STORE (BSWAP) -> sthbrx/stwbrx. if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP && N->getOperand(1).getNode()->hasOneUse() && |
