diff options
Diffstat (limited to 'llvm/lib/Target/Mips')
4 files changed, 49 insertions, 23 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index ea86f48f09a..e79be336362 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -67,13 +67,15 @@ namespace { class MipsAsmBackend : public MCAsmBackend { Triple::OSType OSType; bool IsLittle; // Big or little endian + bool Is64Bit; // 32 or 64 bit words public: - MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle) : - MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle) {} + MipsAsmBackend(const Target &T, Triple::OSType _OSType, + bool _isLittle, bool _is64Bit) + :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { - return createMipsELFObjectWriter(OS, OSType, IsLittle); + return createMipsELFObjectWriter(OS, OSType, IsLittle, Is64Bit); } /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided @@ -208,17 +210,28 @@ public: bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { return true; } -}; +}; // class MipsAsmBackend } // namespace // MCAsmBackend -MCAsmBackend *llvm::createMipsAsmBackendEL(const Target &T, StringRef TT) { +MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) { return new MipsAsmBackend(T, Triple(TT).getOS(), - /*IsLittle*/true); + /*IsLittle*/true, /*Is64Bit*/false); } -MCAsmBackend *llvm::createMipsAsmBackendEB(const Target &T, StringRef TT) { +MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) { return new MipsAsmBackend(T, Triple(TT).getOS(), - /*IsLittle*/false); + /*IsLittle*/false, /*Is64Bit*/false); } + +MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) { + return new MipsAsmBackend(T, Triple(TT).getOS(), + /*IsLittle*/true, /*Is64Bit*/true); +} + +MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) { + return new MipsAsmBackend(T, Triple(TT).getOS(), + /*IsLittle*/false, /*Is64Bit*/true); +} + diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index f12f9af7471..2091bec5008 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -34,7 +34,7 @@ namespace { class MipsELFObjectWriter : public MCELFObjectTargetWriter { public: - MipsELFObjectWriter(uint8_t OSABI); + MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI); virtual ~MipsELFObjectWriter(); @@ -52,15 +52,23 @@ namespace { }; } -MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI) - : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_MIPS, +MipsELFObjectWriter::MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI) + : MCELFObjectTargetWriter(_is64Bit, OSABI, ELF::EM_MIPS, /*HasRelocationAddend*/ false) {} MipsELFObjectWriter::~MipsELFObjectWriter() {} -// FIXME: get the real EABI Version from the Triple. +// FIXME: get the real EABI Version from the Subtarget class. unsigned MipsELFObjectWriter::getEFlags() const { - return ELF::EF_MIPS_NOREORDER | ELF::EF_MIPS_ARCH_32R2; + + // FIXME: We can't tell if we are PIC (dynamic) or CPIC (static) + unsigned Flag = ELF::EF_MIPS_NOREORDER; + + if (is64Bit()) + Flag |= ELF::EF_MIPS_ARCH_64R2; + else + Flag |= ELF::EF_MIPS_ARCH_32R2; + return Flag; } const MCSymbol *MipsELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, @@ -232,8 +240,10 @@ void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm, Relocs[--I] = R->Reloc; } -MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI, - bool IsLittleEndian) { - MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(OSABI); +MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS, + uint8_t OSABI, + bool IsLittleEndian, + bool Is64Bit) { + MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(Is64Bit, OSABI); return createELFObjectWriter(MOTW, OS, IsLittleEndian); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 7be6f81ac88..3c544f6aec9 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -145,13 +145,13 @@ extern "C" void LLVMInitializeMipsTargetMC() { // Register the asm backend. TargetRegistry::RegisterMCAsmBackend(TheMipsTarget, - createMipsAsmBackendEB); + createMipsAsmBackendEB32); TargetRegistry::RegisterMCAsmBackend(TheMipselTarget, - createMipsAsmBackendEL); + createMipsAsmBackendEL32); TargetRegistry::RegisterMCAsmBackend(TheMips64Target, - createMipsAsmBackendEB); + createMipsAsmBackendEB64); TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, - createMipsAsmBackendEL); + createMipsAsmBackendEL64); // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index 2e58f9d1cf6..547ccddd78e 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -39,12 +39,15 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx); -MCAsmBackend *createMipsAsmBackendEB(const Target &T, StringRef TT); -MCAsmBackend *createMipsAsmBackendEL(const Target &T, StringRef TT); +MCAsmBackend *createMipsAsmBackendEB32(const Target &T, StringRef TT); +MCAsmBackend *createMipsAsmBackendEL32(const Target &T, StringRef TT); +MCAsmBackend *createMipsAsmBackendEB64(const Target &T, StringRef TT); +MCAsmBackend *createMipsAsmBackendEL64(const Target &T, StringRef TT); MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI, - bool IsLittleEndian); + bool IsLittleEndian, + bool Is64Bit); } // End llvm namespace // Defines symbolic names for Mips registers. This defines a mapping from |
