diff options
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSchedule.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSchedule.td | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td index aedbed34192..e9f1cb7601c 100644 --- a/llvm/lib/Target/Mips/MipsSchedule.td +++ b/llvm/lib/Target/Mips/MipsSchedule.td @@ -92,8 +92,10 @@ def II_DIVU : InstrItinClass; def II_DIV_D : InstrItinClass; def II_DIV_S : InstrItinClass; def II_DMFC0 : InstrItinClass; +def II_DMFGC0 : InstrItinClass; def II_DMT : InstrItinClass; def II_DMTC0 : InstrItinClass; +def II_DMTGC0 : InstrItinClass; def II_DMFC1 : InstrItinClass; def II_DMTC1 : InstrItinClass; def II_DMOD : InstrItinClass; @@ -128,6 +130,7 @@ def II_EVPE : InstrItinClass; def II_EXT : InstrItinClass; // Any EXT instruction def II_FLOOR : InstrItinClass; def II_FORK : InstrItinClass; +def II_HYPCALL : InstrItinClass; def II_INS : InstrItinClass; // Any INS instruction def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo. def II_J : InstrItinClass; @@ -233,6 +236,8 @@ def II_MFHC0 : InstrItinClass; def II_MFC1 : InstrItinClass; def II_MFHC1 : InstrItinClass; def II_MFC2 : InstrItinClass; +def II_MFGC0 : InstrItinClass; +def II_MFHGC0 : InstrItinClass; def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo def II_MFTR : InstrItinClass; def II_MOD : InstrItinClass; @@ -263,6 +268,8 @@ def II_MTHC0 : InstrItinClass; def II_MTC1 : InstrItinClass; def II_MTHC1 : InstrItinClass; def II_MTC2 : InstrItinClass; +def II_MTGC0 : InstrItinClass; +def II_MTHGC0 : InstrItinClass; def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo def II_MTTR : InstrItinClass; def II_MUL : InstrItinClass; @@ -354,6 +361,12 @@ def II_CACHEE : InstrItinClass; def II_PREFE : InstrItinClass; def II_LLE : InstrItinClass; def II_SCE : InstrItinClass; +def II_TLBGINV : InstrItinClass; +def II_TLBGINVF : InstrItinClass; +def II_TLBGP : InstrItinClass; +def II_TLBGR : InstrItinClass; +def II_TLBGWI : InstrItinClass; +def II_TLBGWR : InstrItinClass; def II_TLBINV : InstrItinClass; def II_TLBINVF : InstrItinClass; def II_WRPGPR : InstrItinClass; @@ -702,5 +715,18 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_CRC32CB , [InstrStage<1, [ALU]>]>, InstrItinData<II_CRC32CH , [InstrStage<1, [ALU]>]>, InstrItinData<II_CRC32CW , [InstrStage<1, [ALU]>]>, - InstrItinData<II_CRC32CD , [InstrStage<1, [ALU]>]> + InstrItinData<II_CRC32CD , [InstrStage<1, [ALU]>]>, + InstrItinData<II_MFGC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MTGC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MFHGC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MTHGC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_HYPCALL , [InstrStage<2, [ALU]>]>, + InstrItinData<II_TLBGINV , [InstrStage<2, [ALU]>]>, + InstrItinData<II_TLBGINVF , [InstrStage<2, [ALU]>]>, + InstrItinData<II_TLBGP , [InstrStage<2, [ALU]>]>, + InstrItinData<II_TLBGR , [InstrStage<2, [ALU]>]>, + InstrItinData<II_TLBWI , [InstrStage<2, [ALU]>]>, + InstrItinData<II_TLBWR , [InstrStage<2, [ALU]>]>, + InstrItinData<II_DMFGC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_DMTGC0 , [InstrStage<2, [ALU]>]> ]>; |
