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-rw-r--r--llvm/lib/Target/Mips/MipsInstructionSelector.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 41856476716..c97fac9d21b 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -160,6 +160,18 @@ bool MipsInstructionSelector::select(MachineInstr &I,
.add(I.getOperand(1));
break;
}
+ case G_PHI: {
+ const unsigned DestReg = I.getOperand(0).getReg();
+ const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
+ const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
+
+ if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
+ return false;
+
+ const TargetRegisterClass *DefRC = &Mips::GPR32RegClass;
+ I.setDesc(TII.get(TargetOpcode::PHI));
+ return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
+ }
case G_STORE:
case G_LOAD:
case G_ZEXTLOAD:
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