1 files changed, 53 insertions, 22 deletions

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 56a9807fc23..21b038e579f 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -1,4 +1,4 @@
-//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
+//===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -17,16 +17,45 @@
 
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
+#include "MCTargetDesc/MipsMCTargetDesc.h"
 #include "Mips.h"
-#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/ISDOpcodes.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/IR/Function.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/CallingConv.h"
+#include "llvm/IR/InlineAsm.h"
+#include "llvm/IR/Type.h"
 #include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
+#include <algorithm>
+#include <cassert>
 #include <deque>
 #include <string>
+#include <utility>
+#include <vector>
 
 namespace llvm {
+
+class Argument;
+class CCState;
+class CCValAssign;
+class FastISel;
+class FunctionLoweringInfo;
+class MachineBasicBlock;
+class MachineFrameInfo;
+class MachineInstr;
+class MipsCCState;
+class MipsFunctionInfo;
+class MipsSubtarget;
+class MipsTargetMachine;
+class TargetLibraryInfo;
+class TargetRegisterClass;
+
   namespace MipsISD {
+
     enum NodeType : unsigned {
       // Start the numbering from where ISD NodeType finishes.
       FIRST_NUMBER = ISD::BUILTIN_OP_END,
@@ -224,17 +253,16 @@ namespace llvm {
       SDL,
       SDR
     };
-  }
+
+  } // ene namespace MipsISD
 
   //===--------------------------------------------------------------------===//
   // TargetLowering Implementation
   //===--------------------------------------------------------------------===//
-  class MipsFunctionInfo;
-  class MipsSubtarget;
-  class MipsCCState;
 
   class MipsTargetLowering : public TargetLowering  {
     bool isMicroMips;
+
   public:
     explicit MipsTargetLowering(const MipsTargetMachine &TM,
                                 const MipsSubtarget &STI);
@@ -256,26 +284,26 @@ namespace llvm {
 
     /// Return the register type for a given MVT, ensuring vectors are treated
     /// as a series of gpr sized integers.
-    virtual MVT getRegisterTypeForCallingConv(MVT VT) const override;
+    MVT getRegisterTypeForCallingConv(MVT VT) const override;
 
     /// Return the register type for a given MVT, ensuring vectors are treated
     /// as a series of gpr sized integers.
-    virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
-                                              EVT VT) const override;
+    MVT getRegisterTypeForCallingConv(LLVMContext &Context,
+                                      EVT VT) const override;
 
     /// Return the number of registers for a given MVT, ensuring vectors are
     /// treated as a series of gpr sized integers.
-    virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
-                                                   EVT VT) const override;
+    unsigned getNumRegistersForCallingConv(LLVMContext &Context,
+                                           EVT VT) const override;
 
     /// Break down vectors to the correct number of gpr sized integers.
-    virtual unsigned getVectorTypeBreakdownForCallingConv(
+    unsigned getVectorTypeBreakdownForCallingConv(
         LLVMContext &Context, EVT VT, EVT &IntermediateVT,
         unsigned &NumIntermediates, MVT &RegisterVT) const override;
 
     /// Return the correct alignment for the current calling convention.
-    virtual unsigned
-    getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override {
+    unsigned getABIAlignmentForCallingConv(Type *ArgTy,
+                                           DataLayout DL) const override {
       if (ArgTy->isVectorTy())
         return std::min(DL.getABITypeAlignment(ArgTy), 8U);
       return DL.getABITypeAlignment(ArgTy);
@@ -461,7 +489,7 @@ namespace llvm {
     /// copyToReg nodes to set up argument registers.
     virtual void
     getOpndList(SmallVectorImpl<SDValue> &Ops,
-                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
+                std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
                 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
                 SDValue Chain) const;
@@ -681,10 +709,13 @@ namespace llvm {
   createMipsSETargetLowering(const MipsTargetMachine &TM,
                              const MipsSubtarget &STI);
 
-  namespace Mips {
-    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
-                             const TargetLibraryInfo *libInfo);
-  }
-}
+namespace Mips {
+
+FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
+                         const TargetLibraryInfo *libInfo);
+
+} // end namespace Mips
+
+} // end namespace llvm
 
-#endif
+#endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H