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-rw-r--r--llvm/lib/Target/Mips/MipsAsmPrinter.cpp18
1 files changed, 0 insertions, 18 deletions
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index c617918e742..51fd13d96fd 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -36,7 +36,6 @@
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/TargetRegistry.h"
@@ -56,23 +55,6 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MipsMCInstLower MCInstLowering(Mang, *MF, *this);
unsigned Opc = MI->getOpcode();
-
- // If target is Mips1, expand double precision load/store to two single
- // precision loads/stores (and delay slot if MI is a load).
- if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
- SmallVector<MCInst, 4> MCInsts;
- const unsigned* SubReg =
- TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
- MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
- Subtarget->isLittle(), SubReg);
-
- for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
- I != MCInsts.end(); ++I)
- OutStreamer.EmitInstruction(*I);
-
- return;
- }
-
MCInst TmpInst0;
MCInstLowering.Lower(MI, TmpInst0);
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