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-rw-r--r--llvm/lib/Target/Mips/Mips64r6InstrInfo.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
index 3a474b204b7..82ec96d85e1 100644
--- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -88,6 +88,8 @@ class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> {
list<Register> Defs = [AT];
}
+class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
+class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@@ -123,6 +125,11 @@ let DecoderNamespace = "Mips32r6_64r6_GP64" in {
def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
}
+let AdditionalPredicates = [NotInMicroMips],
+ DecoderNamespace = "Mips32r6_64r6_PTR64" in {
+ def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
+ def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
+}
let isCodeGenOnly = 1 in {
def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
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