1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index d1f4458233d..cdf12c8d2e4 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -37,19 +37,19 @@ def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
 let DecoderNamespace = "Mips64" in {
 
 multiclass Atomic2Ops64<PatFrag Op> {
-  def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
-               Requires<[NotN64, HasStdEnc]>;
-  def _P8    : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
-               Requires<[IsN64, HasStdEnc]> {
+  def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
+             Requires<[NotN64, HasStdEnc]>;
+  def _P8  : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
+             Requires<[IsN64, HasStdEnc]> {
     let isCodeGenOnly = 1;
   }
 }
 
 multiclass AtomicCmpSwap64<PatFrag Op>  {
-  def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
-               Requires<[NotN64, HasStdEnc]>;
-  def _P8    : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
-               Requires<[IsN64, HasStdEnc]> {
+  def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
+             Requires<[NotN64, HasStdEnc]>;
+  def _P8  : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
+             Requires<[IsN64, HasStdEnc]> {
     let isCodeGenOnly = 1;
   }
 }