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-rw-r--r--llvm/lib/Target/Mips/Mips.td6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 8beb3fb8953..c4b40e24f75 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -33,6 +33,7 @@ def MipsInstrInfo : InstrInfo {
// CPU Directives //
//===----------------------------------------------------------------------===//
+// Not currently supported, but work as SubtargetFeature placeholder.
def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true",
"MipsIII ISA Support">;
@@ -40,8 +41,9 @@ def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true",
// Mips processors supported.
//===----------------------------------------------------------------------===//
-def : Processor<"generic", MipsGenericItineraries, []>;
-//def : Processor<"r4000", MipsR4000Itineraries, [FeatureMipsIII]>;
+def : Processor<"mips1", MipsGenericItineraries, []>;
+def : Processor<"r2000", MipsGenericItineraries, []>;
+def : Processor<"r3000", MipsGenericItineraries, []>;
def Mips : Target {
let InstructionSet = MipsInstrInfo;
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