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Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
-rw-r--r--llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp292
1 files changed, 146 insertions, 146 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index f9d00291419..4fc1293bcbc 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -490,13 +490,13 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
return MCDisassembler::Fail;
// $n
tmp = fieldFromInstruction(insn, 16, NSize);
- MI.addOperand(MCOperand::CreateImm(tmp));
+ MI.addOperand(MCOperand::createImm(tmp));
// $ws
tmp = fieldFromInstruction(insn, 11, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
// $n2
- MI.addOperand(MCOperand::CreateImm(0));
+ MI.addOperand(MCOperand::createImm(0));
return MCDisassembler::Success;
}
@@ -530,12 +530,12 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
MI.setOpcode(Mips::BEQZALC);
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -569,12 +569,12 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
MI.setOpcode(Mips::BNEZALC);
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -611,13 +611,13 @@ static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -655,13 +655,13 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -703,14 +703,14 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
if (HasRt)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -747,12 +747,12 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
}
if (HasRs)
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
- MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
+ MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
- MI.addOperand(MCOperand::CreateImm(Imm));
+ MI.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
@@ -929,7 +929,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -940,7 +940,7 @@ static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -951,7 +951,7 @@ static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -962,7 +962,7 @@ static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -973,7 +973,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1002,7 +1002,7 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1014,7 +1014,7 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1025,7 +1025,7 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1036,7 +1036,7 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1047,7 +1047,7 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1064,12 +1064,12 @@ static DecodeStatus DecodeMem(MCInst &Inst,
if(Inst.getOpcode() == Mips::SC ||
Inst.getOpcode() == Mips::SCD){
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
}
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1084,9 +1084,9 @@ static DecodeStatus DecodeCacheOp(MCInst &Inst,
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
- Inst.addOperand(MCOperand::CreateImm(Hint));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
@@ -1101,9 +1101,9 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
- Inst.addOperand(MCOperand::CreateImm(Hint));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
@@ -1118,9 +1118,9 @@ static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
- Inst.addOperand(MCOperand::CreateImm(Hint));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Hint));
return MCDisassembler::Success;
}
@@ -1134,8 +1134,8 @@ static DecodeStatus DecodeSyncI(MCInst &Inst,
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1149,8 +1149,8 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
// The immediate field of an LD/ST instruction is scaled which means it must
// be multiplied (when decoding) by the size (in bytes) of the instructions'
@@ -1167,19 +1167,19 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
break;
case Mips::LD_B:
case Mips::ST_B:
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::LD_H:
case Mips::ST_H:
- Inst.addOperand(MCOperand::CreateImm(Offset * 2));
+ Inst.addOperand(MCOperand::createImm(Offset * 2));
break;
case Mips::LD_W:
case Mips::ST_W:
- Inst.addOperand(MCOperand::CreateImm(Offset * 4));
+ Inst.addOperand(MCOperand::createImm(Offset * 4));
break;
case Mips::LD_D:
case Mips::ST_D:
- Inst.addOperand(MCOperand::CreateImm(Offset * 8));
+ Inst.addOperand(MCOperand::createImm(Offset * 8));
break;
}
@@ -1218,20 +1218,20 @@ static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
switch (Inst.getOpcode()) {
case Mips::LBU16_MM:
if (Offset == 0xf)
- Inst.addOperand(MCOperand::CreateImm(-1));
+ Inst.addOperand(MCOperand::createImm(-1));
else
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::SB16_MM:
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::LHU16_MM:
case Mips::SH16_MM:
- Inst.addOperand(MCOperand::CreateImm(Offset << 1));
+ Inst.addOperand(MCOperand::createImm(Offset << 1));
break;
case Mips::LW16_MM:
case Mips::SW16_MM:
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
break;
}
@@ -1247,9 +1247,9 @@ static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Mips::SP));
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
}
@@ -1263,9 +1263,9 @@ static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Mips::GP));
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Mips::GP));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
}
@@ -1280,8 +1280,8 @@ static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
== MCDisassembler::Fail)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Mips::SP));
- Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+ Inst.addOperand(MCOperand::createReg(Mips::SP));
+ Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success;
}
@@ -1303,19 +1303,19 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
== MCDisassembler::Fail)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
break;
case Mips::SC_MM:
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
// fallthrough
default:
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
- Inst.addOperand(MCOperand::CreateReg(Reg+1));
+ Inst.addOperand(MCOperand::createReg(Reg+1));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
}
return MCDisassembler::Success;
@@ -1332,9 +1332,9 @@ static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1350,9 +1350,9 @@ static DecodeStatus DecodeFMem(MCInst &Inst,
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1368,9 +1368,9 @@ static DecodeStatus DecodeFMem2(MCInst &Inst,
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1386,9 +1386,9 @@ static DecodeStatus DecodeFMem3(MCInst &Inst,
Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1404,9 +1404,9 @@ static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
- Inst.addOperand(MCOperand::CreateReg(Reg));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1422,12 +1422,12 @@ static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
- Inst.addOperand(MCOperand::CreateReg(Rt));
+ Inst.addOperand(MCOperand::createReg(Rt));
}
- Inst.addOperand(MCOperand::CreateReg(Rt));
- Inst.addOperand(MCOperand::CreateReg(Base));
- Inst.addOperand(MCOperand::CreateImm(Offset));
+ Inst.addOperand(MCOperand::createReg(Rt));
+ Inst.addOperand(MCOperand::createReg(Base));
+ Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
@@ -1439,7 +1439,7 @@ static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
// Currently only hardware register 29 is supported.
if (RegNo != 29)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
+ Inst.addOperand(MCOperand::createReg(Mips::HWR29));
return MCDisassembler::Success;
}
@@ -1452,7 +1452,7 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
;
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1464,7 +1464,7 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1476,7 +1476,7 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1488,7 +1488,7 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1500,7 +1500,7 @@ static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1512,7 +1512,7 @@ static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1524,7 +1524,7 @@ static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1536,7 +1536,7 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1548,7 +1548,7 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1560,7 +1560,7 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
- Inst.addOperand(MCOperand::CreateReg(Reg));
+ Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -1569,7 +1569,7 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1579,7 +1579,7 @@ static DecodeStatus DecodeJumpTarget(MCInst &Inst,
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
- Inst.addOperand(MCOperand::CreateImm(JumpOffset));
+ Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success;
}
@@ -1589,7 +1589,7 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1599,7 +1599,7 @@ static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1608,7 +1608,7 @@ static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1617,7 +1617,7 @@ static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1626,7 +1626,7 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
- Inst.addOperand(MCOperand::CreateImm(BranchOffset));
+ Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success;
}
@@ -1635,7 +1635,7 @@ static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
- Inst.addOperand(MCOperand::CreateImm(JumpOffset));
+ Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success;
}
@@ -1644,11 +1644,11 @@ static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
if (Value == 0)
- Inst.addOperand(MCOperand::CreateImm(1));
+ Inst.addOperand(MCOperand::createImm(1));
else if (Value == 0x7)
- Inst.addOperand(MCOperand::CreateImm(-1));
+ Inst.addOperand(MCOperand::createImm(-1));
else
- Inst.addOperand(MCOperand::CreateImm(Value << 2));
+ Inst.addOperand(MCOperand::createImm(Value << 2));
return MCDisassembler::Success;
}
@@ -1656,7 +1656,7 @@ static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Value << 2));
+ Inst.addOperand(MCOperand::createImm(Value << 2));
return MCDisassembler::Success;
}
@@ -1665,9 +1665,9 @@ static DecodeStatus DecodeLiSimm7(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
if (Value == 0x7F)
- Inst.addOperand(MCOperand::CreateImm(-1));
+ Inst.addOperand(MCOperand::createImm(-1));
else
- Inst.addOperand(MCOperand::CreateImm(Value));
+ Inst.addOperand(MCOperand::createImm(Value));
return MCDisassembler::Success;
}
@@ -1675,7 +1675,7 @@ static DecodeStatus DecodeSimm4(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
return MCDisassembler::Success;
}
@@ -1683,7 +1683,7 @@ static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
return MCDisassembler::Success;
}
@@ -1692,7 +1692,7 @@ static DecodeStatus DecodeLSAImm(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
// We add one to the immediate field as it was encoded as 'imm - 1'.
- Inst.addOperand(MCOperand::CreateImm(Insn + 1));
+ Inst.addOperand(MCOperand::createImm(Insn + 1));
return MCDisassembler::Success;
}
@@ -1703,7 +1703,7 @@ static DecodeStatus DecodeInsSize(MCInst &Inst,
// First we need to grab the pos(lsb) from MCInst.
int Pos = Inst.getOperand(2).getImm();
int Size = (int) Insn - Pos + 1;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}
@@ -1712,19 +1712,19 @@ static DecodeStatus DecodeExtSize(MCInst &Inst,
uint64_t Address,
const void *Decoder) {
int Size = (int) Insn + 1;
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
return MCDisassembler::Success;
}
@@ -1738,7 +1738,7 @@ static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
case 511: DecodedValue = -257; break;
default: DecodedValue = SignExtend32<9>(Insn); break;
}
- Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
+ Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
return MCDisassembler::Success;
}
@@ -1748,13 +1748,13 @@ static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
assert(Insn < 16);
int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
255, 32768, 65535};
- Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
+ Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
return MCDisassembler::Success;
}
static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(Insn << 2));
+ Inst.addOperand(MCOperand::createImm(Insn << 2));
return MCDisassembler::Success;
}
@@ -1773,10 +1773,10 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst,
RegNum = RegLst & 0xf;
for (unsigned i = 0; i < RegNum; i++)
- Inst.addOperand(MCOperand::CreateReg(Regs[i]));
+ Inst.addOperand(MCOperand::createReg(Regs[i]));
if (RegLst & 0x10)
- Inst.addOperand(MCOperand::CreateReg(Mips::RA));
+ Inst.addOperand(MCOperand::createReg(Mips::RA));
return MCDisassembler::Success;
}
@@ -1789,9 +1789,9 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
unsigned RegNum = RegLst & 0x3;
for (unsigned i = 0; i <= RegNum; i++)
- Inst.addOperand(MCOperand::CreateReg(Regs[i]));
+ Inst.addOperand(MCOperand::createReg(Regs[i]));
- Inst.addOperand(MCOperand::CreateReg(Mips::RA));
+ Inst.addOperand(MCOperand::createReg(Mips::RA));
return MCDisassembler::Success;
}
@@ -1805,36 +1805,36 @@ static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
default:
return MCDisassembler::Fail;
case 0:
- Inst.addOperand(MCOperand::CreateReg(Mips::A1));
- Inst.addOperand(MCOperand::CreateReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::A2));
break;
case 1:
- Inst.addOperand(MCOperand::CreateReg(Mips::A1));
- Inst.addOperand(MCOperand::CreateReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::A3));
break;
case 2:
- Inst.addOperand(MCOperand::CreateReg(Mips::A2));
- Inst.addOperand(MCOperand::CreateReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::A3));
break;
case 3:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::S5));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::S5));
break;
case 4:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::S6));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::S6));
break;
case 5:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::A1));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::A1));
break;
case 6:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::A2));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::A2));
break;
case 7:
- Inst.addOperand(MCOperand::CreateReg(Mips::A0));
- Inst.addOperand(MCOperand::CreateReg(Mips::A3));
+ Inst.addOperand(MCOperand::createReg(Mips::A0));
+ Inst.addOperand(MCOperand::createReg(Mips::A3));
break;
}
@@ -1843,6 +1843,6 @@ static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
+ Inst.addOperand(MCOperand::createImm(SignExtend32<23>(Insn) << 2));
return MCDisassembler::Success;
}
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