diff options
Diffstat (limited to 'llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 8912243af09..8c0c181feca 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -16,6 +16,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstBuilder.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCStreamer.h" @@ -589,6 +590,7 @@ static const MCInstrDesc &getInstDesc(unsigned Opcode) { bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); + Inst.setLoc(IDLoc); if (MCID.isBranch() || MCID.isCall()) { @@ -690,6 +692,10 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) { case Mips::LoadImm32Reg: case Mips::LoadAddr32Imm: case Mips::LoadAddr32Reg: + case Mips::SUBi: + case Mips::SUBiu: + case Mips::DSUBi: + case Mips::DSUBiu: return true; default: return false; @@ -705,6 +711,30 @@ void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc, return expandLoadAddressImm(Inst, IDLoc, Instructions); case Mips::LoadAddr32Reg: return expandLoadAddressReg(Inst, IDLoc, Instructions); + case Mips::SUBi: + Instructions.push_back(MCInstBuilder(Mips::ADDi) + .addReg(Inst.getOperand(0).getReg()) + .addReg(Inst.getOperand(1).getReg()) + .addImm(-Inst.getOperand(2).getImm())); + return; + case Mips::SUBiu: + Instructions.push_back(MCInstBuilder(Mips::ADDiu) + .addReg(Inst.getOperand(0).getReg()) + .addReg(Inst.getOperand(1).getReg()) + .addImm(-Inst.getOperand(2).getImm())); + return; + case Mips::DSUBi: + Instructions.push_back(MCInstBuilder(Mips::DADDi) + .addReg(Inst.getOperand(0).getReg()) + .addReg(Inst.getOperand(1).getReg()) + .addImm(-Inst.getOperand(2).getImm())); + return; + case Mips::DSUBiu: + Instructions.push_back(MCInstBuilder(Mips::DADDiu) + .addReg(Inst.getOperand(0).getReg()) + .addReg(Inst.getOperand(1).getReg()) + .addImm(-Inst.getOperand(2).getImm())); + return; } } |
