diff options
Diffstat (limited to 'llvm/lib/Target/IA64')
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelLowering.cpp | 9 |
2 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 5add5d6ed5f..79252bcbaef 100644 --- a/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -453,15 +453,14 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) { } */ - case ISD::LOAD: - case ISD::LOADX: { // FIXME: load -1, not 1, for bools? - SDOperand Chain = N->getOperand(0); - SDOperand Address = N->getOperand(1); + case ISD::LOAD: { // FIXME: load -1, not 1, for bools? + LoadSDNode *LD = cast<LoadSDNode>(N); + SDOperand Chain = LD->getChain(); + SDOperand Address = LD->getBasePtr(); AddToISelQueue(Chain); AddToISelQueue(Address); - MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ? - N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT(); + MVT::ValueType TypeBeingLoaded = LD->getLoadVT(); unsigned Opc; switch (TypeBeingLoaded) { default: diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp index 47421a516f5..450a47bfec8 100644 --- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp +++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp @@ -133,7 +133,7 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const { static bool isFloatingPointZero(SDOperand Op) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); - else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { + else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { // Maybe this has already been legalized into the constant pool? if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) @@ -226,7 +226,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { //from this parameter SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); argt = newroot = DAG.getLoad(getValueType(I->getType()), - DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); + DAG.getEntryNode(), FIN, NULL, 0); } ++count; DAG.setRoot(newroot.getValue(1)); @@ -583,8 +583,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { } case ISD::VAARG: { MVT::ValueType VT = getPointerTy(); + SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), - Op.getOperand(2)); + SV->getValue(), SV->getOffset()); // Increment the pointer, VAList, to the next vaarg SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, DAG.getConstant(MVT::getSizeInBits(VT)/8, @@ -593,7 +594,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, Op.getOperand(1), Op.getOperand(2)); // Load the actual argument out of the pointer VAList - return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0)); + return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the |
