diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 8 |
5 files changed, 16 insertions, 16 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 3ab796d01c4..60c933be307 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -300,7 +300,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1, MachineBasicBlock::iterator I(I1), End(I2); // At O3 we got better results (dhrystone) by being more conservative here. if (!ShouldCombineAggressively) - End = llvm::next(MachineBasicBlock::iterator(I2)); + End = std::next(MachineBasicBlock::iterator(I2)); IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal(); unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg(); // Track killed operands. If we move across an instruction that kills our @@ -464,7 +464,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { /// false if the combine must be inserted at the returned instruction. MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1, bool &DoInsertAtI1) { - MachineBasicBlock::iterator I2 = llvm::next(MachineBasicBlock::iterator(I1)); + MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1)); unsigned I1DestReg = I1->getOperand(0).getReg(); for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End; diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 2b04f25dd67..0ea13d4c80e 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -144,14 +144,14 @@ bool HexagonFrameLowering::hasTailCall(MachineBasicBlock &MBB) const { void HexagonFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = std::prev(MBB.end()); DebugLoc dl = MBBI->getDebugLoc(); // // Only insert deallocframe if we need to. Also at -O0. See comment // in emitPrologue above. // if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = std::prev(MBB.end()); MachineBasicBlock::iterator MBBI_end = MBB.end(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); @@ -170,7 +170,7 @@ void HexagonFrameLowering::emitEpilogue(MachineFunction &MF, // Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC // instruction if we encounter it. MachineBasicBlock::iterator BeforeJMPR = - MBB.begin() == MBBI ? MBBI : prior(MBBI); + MBB.begin() == MBBI ? MBBI : std::prev(MBBI); if (BeforeJMPR != MBBI && BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) { // Remove the JMPR node. @@ -190,7 +190,7 @@ void HexagonFrameLowering::emitEpilogue(MachineFunction &MF, // DEALLOCFRAME instruction after it. MachineBasicBlock::iterator Term = MBB.getFirstTerminator(); MachineBasicBlock::iterator I = - Term == MBB.begin() ? MBB.end() : prior(Term); + Term == MBB.begin() ? MBB.end() : std::prev(Term); if (I != MBB.end() && I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4) return; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index fccbcb3d703..c94be7ec573 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -907,7 +907,7 @@ bool HexagonHardwareLoops::isDead(const MachineInstr *MI, // this instruction is dead: both it (and the phi node) can be removed. use_nodbg_iterator I = MRI->use_nodbg_begin(Reg); use_nodbg_iterator End = MRI->use_nodbg_end(); - if (llvm::next(I) != End || !I.getOperand().getParent()->isPHI()) + if (std::next(I) != End || !I.getOperand().getParent()->isPHI()) return false; MachineInstr *OnePhi = I.getOperand().getParent(); @@ -920,7 +920,7 @@ bool HexagonHardwareLoops::isDead(const MachineInstr *MI, use_nodbg_iterator nextJ; for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J != End; J = nextJ) { - nextJ = llvm::next(J); + nextJ = std::next(J); MachineOperand &Use = J.getOperand(); MachineInstr *UseMI = Use.getParent(); @@ -954,7 +954,7 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) { MachineRegisterInfo::use_iterator nextI; for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) { - nextI = llvm::next(I); // I is invalidated by the setReg + nextI = std::next(I); // I is invalidated by the setReg MachineOperand &Use = I.getOperand(); MachineInstr *UseMI = Use.getParent(); if (UseMI == MI) @@ -1162,7 +1162,7 @@ bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI, // Out of order. unsigned PredR = CmpI->getOperand(0).getReg(); bool FoundBump = false; - instr_iterator CmpIt = CmpI, NextIt = llvm::next(CmpIt); + instr_iterator CmpIt = CmpI, NextIt = std::next(CmpIt); for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) { MachineInstr *In = &*I; for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) { @@ -1176,7 +1176,7 @@ bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI, if (In == BumpI) { instr_iterator After = BumpI; instr_iterator From = CmpI; - BB->splice(llvm::next(After), BB, From); + BB->splice(std::next(After), BB, From); FoundBump = true; break; } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index fff51dda679..8d4a9680b88 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -147,7 +147,7 @@ HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) { MachineBasicBlock *NextBB = - llvm::next(MachineFunction::iterator(&MBB)); + std::next(MachineFunction::iterator(&MBB)); if (NewTBB == NextBB) { ReverseBranchCondition(Cond); RemoveBranch(MBB); diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index e9d42f3b490..976ff2b0f5a 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -237,20 +237,20 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) { // instruction stream until we find the nearest boundary. MachineBasicBlock::iterator I = RegionEnd; for(;I != MBB->begin(); --I, --RemainingCount) { - if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn)) + if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn)) break; } I = MBB->begin(); // Skip empty scheduling regions. if (I == RegionEnd) { - RegionEnd = llvm::prior(RegionEnd); + RegionEnd = std::prev(RegionEnd); --RemainingCount; continue; } // Skip regions with one instruction. - if (I == llvm::prior(RegionEnd)) { - RegionEnd = llvm::prior(RegionEnd); + if (I == std::prev(RegionEnd)) { + RegionEnd = std::prev(RegionEnd); continue; } |
